Lines Matching refs:UINT64
105 UINT64 IsUnified : 1;
106 UINT64 Attributes : 2;
107 UINT64 Associativity:8;
108 UINT64 LineSize:8;
109 UINT64 Stride:8;
110 UINT64 StoreLatency:8;
111 UINT64 StoreHint:8;
112 UINT64 LoadHint:8;
120 UINT64 CacheSize:32;
121 UINT64 AliasBoundary:8;
122 UINT64 TagLsBits:8;
123 UINT64 TagMsBits:8;
290 UINT64 ThreadId : 16; ///< The thread identifier of the logical
293 UINT64 Reserved1: 16;
294 UINT64 CoreId: 16; ///< The core identifier of the logical processor
298 UINT64 Reserved2: 16;
303 UINT64 LogicalAddress : 16; ///< Logical address: geographical address
309 UINT64 Reserved1: 16;
310 UINT64 Reserved2: 32;
484 UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number
487 UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the
490 UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the
492 UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the
498 UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is
500 UINT64 EntriesReduction:1; ///< Flag denoting whether installed
567 UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware
570 UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer
573 UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number
575 UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the
577 UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely
580 UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the
583 UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the
586 UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the
590 UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the
595 UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting
598 UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number
600 UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the
609 UINT64 Reserved:32;
988 UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical
992 UINT64 ThreadsPerCore:8; ///< Number of threads per core.
993 UINT64 Reserved1:8;
994 UINT64 CoresPerProcessor:8; ///< Total number of cores on this
996 UINT64 Reserved2:8;
997 UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package
1006 UINT64 Reserved3:8;
1010 UINT64 ThreadId:16; ///< The thread identifier of the logical
1014 UINT64 Reserved1:16;
1015 UINT64 CoreId:16; ///< The core identifier of the logical processor
1019 UINT64 Reserved2:16;
1023 UINT64 LogicalAddress:16; ///< Geographical address of the logical
1028 UINT64 Reserved:48;
1066 UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the
1068 UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range
1071 UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the
1073 UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit
1077 UINT64 Reserved:32;
1136 UINT64 Reserved1:36;
1137 UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented
1156 UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins
1167 UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple
1190 UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state
1209 UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented.
1216 UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS
1225 UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented.
1234 UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic
1246 UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous
1258 UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic
1274 UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable
1292 UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch
1300 UINT64 Reserved2:4;
1301 UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL
1307 UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling
1329 UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw
1336 UINT64 EnableEnvNotification:1; ///< Bit55, Enable external
1364 UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on
1374 UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management
1381 UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,
1387 UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the
1402 UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When
1415 UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT
1427 UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When
1436 UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When
1570 UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD)
1573 UINT64 Reserved1:8;
1574 UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the
1576 UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD)
1584 UINT64 Reserved2:16;
1696 UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for
1699 UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for
1702 UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is
1706 UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is
1710 UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available
1714 UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available
1718 UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is
1722 UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is
1725 UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is
1728 UINT64 Reserved:16;
1741 UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused
1750 UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the
1753 UINT64 Reserved1:2;
1754 …UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache lin…
1755 …UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line.
1756 UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache
1758 UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the
1761 UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache
1766 UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check
1769 UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of
1772 UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the
1775 UINT64 Reserved2:1;
1776 UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was
1780 UINT64 Reserved3:8;
1781 UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache
1783 UINT64 Reserved4:2;
1785 UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value
1793 UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the
1796 UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The
1801 UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the
1805 UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit
1809 UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:
1814 UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This
1819 UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This
1824 UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer.
1833 UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation
1835 UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the
1837 UINT64 Reserved1 :1;
1838 UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the
1841 UINT64 Reserved2 :4;
1843 UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data
1846 UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction
1849 UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data
1852 UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction
1855 UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that
1870 UINT64 Reserved3:30;
1871 UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value
1879 UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the
1882 UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The
1887 UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the
1890 UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit
1894 UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:
1899 UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This
1904 UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This
1909 UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer.
2220 UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory
2228 UINT64 TestPhase:8; ///< Defines which phase of the processor
2249 UINT64 TestControl:47; ///< This is an ordered implementation-specific
2292 UINT64 ControlSupport:1; ///< This bit defines if an implementation
2309 UINT64 Reserved:16;
2313 UINT64 Attributes:8; ///< Specifies the memory attributes that are
2323 UINT64 Reserved:8;
2324 UINT64 TestControl:48; ///< Is the self-test control word
2662 UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this
2671 UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error
2677 UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired
2683 UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure
2698 UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure
2712 UINT64 Reserved:32; ///< Reserved 47:16 Reserved
2714 UINT64 ImplSpec:16; ///< Bit63:48, Processor specific error injection capabilities.
2718 UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the
2728 UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used
2733 UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the
2739 UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to
2754 UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a
2771 UINT64 Reserved1:22;
2773 UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the
2781 UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be
2794 UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege
2808 UINT64 Reserved2:24;
2817 UINT64 TrigerAddress;
2818 UINT64 VirtualPageNumber:52;
2819 UINT64 Reserved1:8;
2820 UINT64 RegionId:24;
2821 UINT64 Reserved2:40;
3012 UINT64 Registration:1;
3013 UINT64 ProbeInterrupt:1;
3014 UINT64 Reserved:62;
3084 UINT64 Reserved1:8;
3085 UINT64 Opcode:1;
3086 UINT64 Reserved:53;