745   VOID    *PageTable;  in Gen4GPageTable()  local
775   PageTable = AllocatePageTableMemory (ExtraPages + 5 + PagesNeeded);  in Gen4GPageTable()
776   ASSERT (PageTable != NULL);  in Gen4GPageTable()
778   PageTable = (VOID *)((UINTN)PageTable + EFI_PAGES_TO_SIZE (ExtraPages));  in Gen4GPageTable()
779   Pte = (UINT64*)PageTable;  in Gen4GPageTable()
790 …Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32BitPageTable ? IA32_PAE_PDPTE_A…  in Gen4GPageTable()
802     Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);  in Gen4GPageTable()
804     Pdpte = (UINT64*)PageTable;  in Gen4GPageTable()
832   return (UINT32)(UINTN)PageTable;  in Gen4GPageTable()
845   IN      UINT64                    *PageTable,  in SetCacheability()  argument
859     ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
860     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);  in SetCacheability()
864   ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
865   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);  in SetCacheability()
873   if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {  in SetCacheability()
883       NewPageTable[Index] = PageTable[PTIndex];  in SetCacheability()
891     PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS;  in SetCacheability()
894   ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
895   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);  in SetCacheability()
898   ASSERT (PageTable[PTIndex] & IA32_PG_P);  in SetCacheability()
899   PageTable[PTIndex] &= ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_PG_WT)));  in SetCacheability()
900   PageTable[PTIndex] |= (UINT64)Cacheability;  in SetCacheability()