Lines Matching refs:ptr
29 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, in NoBarrier_CompareAndSwap() argument
33 reinterpret_cast<volatile LONG*>(ptr), in NoBarrier_CompareAndSwap()
39 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, in NoBarrier_AtomicExchange() argument
42 reinterpret_cast<volatile LONG*>(ptr), in NoBarrier_AtomicExchange()
47 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, in Barrier_AtomicIncrement() argument
50 reinterpret_cast<volatile LONG*>(ptr), in Barrier_AtomicIncrement()
54 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, in NoBarrier_AtomicIncrement() argument
56 return Barrier_AtomicIncrement(ptr, increment); in NoBarrier_AtomicIncrement()
69 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, in Acquire_CompareAndSwap() argument
72 return NoBarrier_CompareAndSwap(ptr, old_value, new_value); in Acquire_CompareAndSwap()
75 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, in Release_CompareAndSwap() argument
78 return NoBarrier_CompareAndSwap(ptr, old_value, new_value); in Release_CompareAndSwap()
81 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) { in NoBarrier_Store() argument
82 *ptr = value; in NoBarrier_Store()
85 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) { in Acquire_Store() argument
86 NoBarrier_AtomicExchange(ptr, value); in Acquire_Store()
90 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) { in Release_Store() argument
91 *ptr = value; // works w/o barrier for current Intel chips as of June 2005 in Release_Store()
95 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) { in NoBarrier_Load() argument
96 return *ptr; in NoBarrier_Load()
99 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) { in Acquire_Load() argument
100 Atomic32 value = *ptr; in Acquire_Load()
104 inline Atomic32 Release_Load(volatile const Atomic32* ptr) { in Release_Load() argument
106 return *ptr; in Release_Load()
115 inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, in NoBarrier_CompareAndSwap() argument
119 reinterpret_cast<volatile PVOID*>(ptr), in NoBarrier_CompareAndSwap()
124 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, in NoBarrier_AtomicExchange() argument
127 reinterpret_cast<volatile PVOID*>(ptr), in NoBarrier_AtomicExchange()
132 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, in Barrier_AtomicIncrement() argument
135 reinterpret_cast<volatile LONGLONG*>(ptr), in Barrier_AtomicIncrement()
139 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, in NoBarrier_AtomicIncrement() argument
141 return Barrier_AtomicIncrement(ptr, increment); in NoBarrier_AtomicIncrement()
144 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) { in NoBarrier_Store() argument
145 *ptr = value; in NoBarrier_Store()
148 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) { in Acquire_Store() argument
149 NoBarrier_AtomicExchange(ptr, value); in Acquire_Store()
153 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) { in Release_Store() argument
154 *ptr = value; // works w/o barrier for current Intel chips as of June 2005 in Release_Store()
164 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) { in NoBarrier_Load() argument
165 return *ptr; in NoBarrier_Load()
168 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) { in Acquire_Load() argument
169 Atomic64 value = *ptr; in Acquire_Load()
173 inline Atomic64 Release_Load(volatile const Atomic64* ptr) { in Release_Load() argument
175 return *ptr; in Release_Load()
178 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, in Acquire_CompareAndSwap() argument
181 return NoBarrier_CompareAndSwap(ptr, old_value, new_value); in Acquire_CompareAndSwap()
184 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, in Release_CompareAndSwap() argument
187 return NoBarrier_CompareAndSwap(ptr, old_value, new_value); in Release_CompareAndSwap()