Lines Matching refs:IntRegs
529 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
544 def IntRegs : RegisterClass<"SP", [i32], 32,
571 associated register classes. The order of registers in ``IntRegs`` reflects
572 the order in the definition of ``IntRegs`` in the target description file.
576 // IntRegs Register Class...
577 static const unsigned IntRegs[] = {
596 // IntRegs Sub-register Classess...
601 // IntRegs Super-register Classess...
606 // IntRegs Register Class sub-classes...
611 // IntRegs Register Class super-classes...
618 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
761 target description file (``IntRegs``).
765 def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
776 let MIOperandInfo = (ops IntRegs, IntRegs);
793 def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
808 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
812 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
861 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1227 def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1291 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)