Lines Matching refs:OperIdx
283 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
326 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
328 MachineOperand &MO = MI->getOperand(OperIdx); in addPhysRegDeps()
353 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
365 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg())); in addPhysRegDeps()
370 addPhysRegDataDeps(SU, OperIdx); in addPhysRegDeps()
397 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg)); in addPhysRegDeps()
421 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { in addVRegDefDeps() argument
423 MachineOperand &MO = MI->getOperand(OperIdx); in addVRegDefDeps()
462 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use, in addVRegDefDeps()
506 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
530 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { in addVRegUseDeps() argument
532 const MachineOperand &MO = MI->getOperand(OperIdx); in addVRegUseDeps()
537 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU)); in addVRegUseDeps()