Lines Matching refs:IsZExt
160 bool WantResult = true, bool IsZExt = false);
180 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
192 bool IsZExt = false);
196 bool IsZExt = false);
220 uint64_t Imm, bool IsZExt = true);
224 uint64_t Imm, bool IsZExt = true);
228 uint64_t Imm, bool IsZExt = false);
270 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
277 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
1083 bool WantResult, bool IsZExt) { in emitAddSub() argument
1094 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
1098 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
1131 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1135 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue(); in emitAddSub()
1229 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1398 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) { in emitCmp() argument
1413 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1421 bool IsZExt) { in emitICmp() argument
1423 IsZExt) != 0; in emitICmp()
1468 bool SetFlags, bool WantResult, bool IsZExt) { in emitAdd() argument
1470 IsZExt); in emitAdd()
1498 bool SetFlags, bool WantResult, bool IsZExt) { in emitSub() argument
1500 IsZExt); in emitSub()
3744 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
3745 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
3831 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext() argument
3839 if (IsZExt) { in emiti1Ext()
3932 bool IsZExt) { in emitLSL_ri() argument
3957 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
3996 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri()
4039 bool IsZExt) { in emitLSR_ri() argument
4064 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4096 if (Shift >= SrcBits && IsZExt) in emitLSR_ri()
4101 if (!IsZExt) { in emitLSR_ri()
4102 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4108 IsZExt = true; in emitLSR_ri()
4117 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri()
4160 bool IsZExt) { in emitASR_ri() argument
4185 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4217 if (Shift >= SrcBits && IsZExt) in emitASR_ri()
4226 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri()
4241 bool IsZExt) { in emitIntExt() argument
4261 return emiti1Ext(SrcReg, DestVT, IsZExt); in emitIntExt()
4264 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4266 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4271 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4273 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4278 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4366 bool IsZExt = isa<ZExtInst>(I); in optimizeIntExtLoad() local
4374 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4383 if (IsZExt) { in optimizeIntExtLoad()
4423 bool IsZExt = isa<ZExtInst>(I); in selectIntExt() local
4425 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4448 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4521 bool IsZExt = true; in selectMul() local
4527 IsZExt = true; in selectMul()
4536 IsZExt = false; in selectMul()
4548 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4587 bool IsZExt = I->getOpcode() != Instruction::AShr; in selectShift() local
4594 IsZExt = true; in selectShift()
4603 IsZExt = false; in selectShift()
4617 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4620 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4623 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()