Lines Matching refs:ShiftImm
170 uint64_t ShiftImm, bool SetFlags = false,
175 uint64_t ShiftImm, bool SetFlags = false,
201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
209 uint64_t ShiftImm);
1277 unsigned ShiftImm; in emitAddSub_ri() local
1279 ShiftImm = 0; in emitAddSub_ri()
1281 ShiftImm = 12; in emitAddSub_ri()
1310 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1318 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1326 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1351 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
1359 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx() argument
1366 if (ShiftImm >= 4) in emitAddSub_rx()
1394 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
1514 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs() argument
1516 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true, in emitSubs_rs()
1653 uint64_t ShiftImm) { in emitLogicalOp_rs() argument
1663 if (ShiftImm >= RetVT.getSizeInBits()) in emitLogicalOp_rs()
1685 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitLogicalOp_rs()