Lines Matching refs:SINT_TO_FP
173 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
174 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
175 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
470 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
551 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
560 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); in AArch64TargetLowering()
562 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); in AArch64TargetLowering()
565 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote); in AArch64TargetLowering()
567 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); in AArch64TargetLowering()
570 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
572 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom); in AArch64TargetLowering()
576 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); in AArch64TargetLowering()
2001 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
2034 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
2396 case ISD::SINT_TO_FP: in LowerOperation()
7676 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF; in performIntToFpCombine()
7765 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
7807 bool IsSigned = Opc == ISD::SINT_TO_FP; in performFDivCombine()
9856 case ISD::SINT_TO_FP: in PerformDAGCombine()