Lines Matching refs:b00
961 let Inst{20-19} = 0b00;
989 let Inst{20-19} = 0b00;
1373 let Inst{15-14} = 0b00;
2236 let Inst{11-10} = 0b00;
2474 let Inst{25-24} = 0b00;
2489 let Inst{25-24} = 0b00;
2586 let Inst{25-24} = 0b00;
2664 let Inst{25-24} = 0b00;
2736 let Inst{25-24} = 0b00;
2808 let Inst{25-24} = 0b00;
2880 let Inst{25-24} = 0b00;
2954 let Inst{25-24} = 0b00;
3007 let Inst{25-24} = 0b00;
3011 let Inst{11-10} = 0b00;
3066 let Inst{25-24} = 0b00;
3159 let Inst{25-24} = 0b00;
3534 let Inst{30-29} = 0b00;
3555 let Inst{30-29} = 0b00;
3583 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3589 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3629 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3638 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3712 let Inst{23-22} = 0b00; // 32-bit FPR flag
3728 let Inst{23-22} = 0b00; // 32-bit FPR flag
3752 let Inst{23-22} = 0b00; // 32-bit FPR flag
3779 let Inst{23-22} = 0b00; // 32-bit FPR flag
3860 def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> {
3866 def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> {
3872 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3874 let Inst{23-22} = 0b00; // 32-bit FPR flag
3877 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3882 def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> {
3888 def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> {
3894 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3896 let Inst{23-22} = 0b00; // 32-bit FPR flag
3899 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3942 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3950 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3954 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3958 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3990 let Inst{23-22} = 0b00; // 32-bit size flag
4032 let Inst{23-22} = 0b00; // 32-bit size flag
4051 let Inst{23-22} = 0b00; // 32-bit size flag
4095 let Inst{23-22} = 0b00; // 32-bit size flag
4161 let Inst{23-22} = 0b00;
4166 let Inst{23-22} = 0b00;
4219 let Inst{23-22} = 0b00;
4262 let Inst{23-22} = 0b00;
4295 let Inst{23-22} = 0b00;
4453 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
4456 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4475 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
4478 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4496 def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64,
4500 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
4622 let Inst{18-17} = 0b00;
4647 let Inst{18-17} = 0b00;
4657 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4660 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4663 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4666 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4669 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
4672 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4697 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4699 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4715 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4718 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4721 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4724 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4727 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
4730 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4737 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, 0b00, V64,
4741 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
4745 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
4749 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4753 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64,
4757 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
4766 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, 0b00, V64,
4769 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
4772 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
4775 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4778 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64,
4781 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
4784 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, 0b00, V128,
4791 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4794 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4797 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4800 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4803 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64,
4806 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4809 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, 0b00, V128,
4818 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, 0b00, V64,
4821 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, 0b00, V128,
4830 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64,
4833 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4836 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
4839 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4856 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4859 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4862 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4870 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4873 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4889 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4892 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4895 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4910 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
4913 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4916 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4968 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4971 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
5013 let Inst{18-17} = 0b00;
5023 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, 0b00, opc, V64,
5026 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, 0b00, opc, V128,
5029 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, 0b00, opc, V64,
5032 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128,
5035 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, 0b00, opc, V64,
5038 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, 0b00, opc, V128,
5041 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
5058 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, 0b00, opc, V64,
5061 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, 0b00, opc, V128,
5064 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128,
5197 let Inst{11-10} = 0b00;
5223 let Inst{11-10} = 0b00;
5722 def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
5739 def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
5814 let Inst{18-17} = 0b00;
5856 let Inst{18-17} = 0b00;
5878 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
5886 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b00, opc, FPR64, asm, "0.0">;
5887 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, 0b00, opc, FPR32, asm, "0.0">;
5907 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
5915 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,[]>;
5916 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
5924 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,
5926 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
5937 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
5939 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm,
5941 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
5942 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>;
5957 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5969 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm,
5971 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
5972 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
6042 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
6044 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
6055 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
6057 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
6373 let Inst{11-10} = 0b00;
6394 let Inst{11-10} = 0b00;
6405 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
6413 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
6449 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6457 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6790 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b00, opc,
6803 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b00, opc,
6854 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc,
6947 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b00, opc, V64, V64,
6956 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b00, opc,
6994 def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc,
8299 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
8311 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
8322 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
8342 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
8372 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
8384 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
8394 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
8414 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
8624 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8626 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8641 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8644 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
9269 let Inst{11-10} = 0b00;
9383 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseCAS<order, "b", GPR32>;
9398 let Sz = 0b00, Acq = Acq, Rel = Rel in
9424 let Inst{11-10} = 0b00;
9430 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseSWP<order, "b", GPR32>;
9456 let Inst{11-10} = 0b00;
9463 let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in