Lines Matching refs:isSub

1309 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1318   let Inst{30}    = isSub;
1326 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1328     : BaseBaseAddSubCarry<isSub, regtype, asm,
1331 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1333     : BaseBaseAddSubCarry<isSub, regtype, asm,
1339 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1341   def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1345   def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1351   def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1356   def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1430 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1442   let Inst{15}    = isSub;
1448 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1450   def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1456   def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1463 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1465   : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1621 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1631   let Inst{30}    = isSub;
1647 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1662   let Inst{30}    = isSub;
1675 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1687   let Inst{30}    = isSub;
1701 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1712   let Inst{30}    = isSub;
1733 multiclass AddSub<bit isSub, string mnemonic, string alias,
1742   def Wri  : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1747   def Xri  : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1757   def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1761   def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1769   def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1773   def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1779   def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1814 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
1818   def Wri  : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1822   def Xri  : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1832   def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1836   def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1843   def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1847   def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1853   def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
4065 class BaseThreeOperandFPData<bit isNegated, bit isSub,
4077   let Inst{15}    = isSub;
4083 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
4085   def Hrrr : BaseThreeOperandFPData<isNegated, isSub, FPR16, asm,
4092   def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
4098   def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,