Lines Matching refs:b00
443 defm MOVN : MoveImmediate<0b00, "movn">;
703 defm LSLV : Shift<0b00, "lsl", shl>;
801 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
806 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
886 defm AND : LogicalImm<0b00, "and", and, "bic">;
903 defm AND : LogicalReg<0b00, 0, "and", and>;
904 defm BIC : LogicalReg<0b00, 1, "bic",
1005 defm SBFM : BitfieldImm<0b00, "sbfm">;
1112 defm CSEL : CondSelect<0, 0b00, "csel">;
1116 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1275 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1279 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1294 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1296 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1303 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1305 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1312 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1314 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1322 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1324 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1333 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1339 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1343 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1350 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1351 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1511 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1523 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1607 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1650 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1654 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1679 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1681 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1700 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1712 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1721 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1861 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1865 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1902 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1909 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1910 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1919 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1923 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1930 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1931 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1934 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1944 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1948 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1955 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1956 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1959 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1971 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1973 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1978 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1980 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1985 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1987 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1992 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1994 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
2002 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
2003 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
2004 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
2005 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
2009 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
2010 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
2011 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
2012 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
2013 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
2103 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2106 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2109 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2112 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2115 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2118 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2121 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2123 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2127 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2202 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2205 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2208 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2211 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2214 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2217 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2220 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2223 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2226 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2315 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2316 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2318 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2319 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2323 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2324 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2325 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2326 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2327 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2328 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2329 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2331 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2332 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2377 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2378 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2379 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2380 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2381 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2382 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2383 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2385 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2386 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2435 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2440 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2445 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2450 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2455 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2460 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2479 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2485 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2493 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2494 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2497 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2498 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2775 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2847 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2878 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
3030 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
3037 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
4445 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4485 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
5083 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
5087 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
5091 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
5095 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
5167 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5253 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5257 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5261 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;