Lines Matching refs:def
23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
34 def subo64 : SubRegIndex<64>;
36 def dsub0 : SubRegIndex<64>;
37 def dsub1 : SubRegIndex<64>;
38 def dsub2 : SubRegIndex<64>;
39 def dsub3 : SubRegIndex<64>;
41 def qsub0 : SubRegIndex<128>;
42 def qsub1 : SubRegIndex<128>;
43 def qsub2 : SubRegIndex<128>;
44 def qsub3 : SubRegIndex<128>;
48 def vreg : RegAltNameIndex;
49 def vlist1 : RegAltNameIndex;
55 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
56 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
57 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
58 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
59 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
60 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
61 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
62 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
63 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
64 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
65 def W10 : AArch64Reg<10, "w10">, DwarfRegNum<[10]>;
66 def W11 : AArch64Reg<11, "w11">, DwarfRegNum<[11]>;
67 def W12 : AArch64Reg<12, "w12">, DwarfRegNum<[12]>;
68 def W13 : AArch64Reg<13, "w13">, DwarfRegNum<[13]>;
69 def W14 : AArch64Reg<14, "w14">, DwarfRegNum<[14]>;
70 def W15 : AArch64Reg<15, "w15">, DwarfRegNum<[15]>;
71 def W16 : AArch64Reg<16, "w16">, DwarfRegNum<[16]>;
72 def W17 : AArch64Reg<17, "w17">, DwarfRegNum<[17]>;
73 def W18 : AArch64Reg<18, "w18">, DwarfRegNum<[18]>;
74 def W19 : AArch64Reg<19, "w19">, DwarfRegNum<[19]>;
75 def W20 : AArch64Reg<20, "w20">, DwarfRegNum<[20]>;
76 def W21 : AArch64Reg<21, "w21">, DwarfRegNum<[21]>;
77 def W22 : AArch64Reg<22, "w22">, DwarfRegNum<[22]>;
78 def W23 : AArch64Reg<23, "w23">, DwarfRegNum<[23]>;
79 def W24 : AArch64Reg<24, "w24">, DwarfRegNum<[24]>;
80 def W25 : AArch64Reg<25, "w25">, DwarfRegNum<[25]>;
81 def W26 : AArch64Reg<26, "w26">, DwarfRegNum<[26]>;
82 def W27 : AArch64Reg<27, "w27">, DwarfRegNum<[27]>;
83 def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>;
84 def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>;
85 def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>;
86 def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
87 def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>;
90 def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>;
91 def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>;
92 def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>;
93 def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>;
94 def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>;
95 def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>;
96 def X6 : AArch64Reg<6, "x6", [W6]>, DwarfRegAlias<W6>;
97 def X7 : AArch64Reg<7, "x7", [W7]>, DwarfRegAlias<W7>;
98 def X8 : AArch64Reg<8, "x8", [W8]>, DwarfRegAlias<W8>;
99 def X9 : AArch64Reg<9, "x9", [W9]>, DwarfRegAlias<W9>;
100 def X10 : AArch64Reg<10, "x10", [W10]>, DwarfRegAlias<W10>;
101 def X11 : AArch64Reg<11, "x11", [W11]>, DwarfRegAlias<W11>;
102 def X12 : AArch64Reg<12, "x12", [W12]>, DwarfRegAlias<W12>;
103 def X13 : AArch64Reg<13, "x13", [W13]>, DwarfRegAlias<W13>;
104 def X14 : AArch64Reg<14, "x14", [W14]>, DwarfRegAlias<W14>;
105 def X15 : AArch64Reg<15, "x15", [W15]>, DwarfRegAlias<W15>;
106 def X16 : AArch64Reg<16, "x16", [W16]>, DwarfRegAlias<W16>;
107 def X17 : AArch64Reg<17, "x17", [W17]>, DwarfRegAlias<W17>;
108 def X18 : AArch64Reg<18, "x18", [W18]>, DwarfRegAlias<W18>;
109 def X19 : AArch64Reg<19, "x19", [W19]>, DwarfRegAlias<W19>;
110 def X20 : AArch64Reg<20, "x20", [W20]>, DwarfRegAlias<W20>;
111 def X21 : AArch64Reg<21, "x21", [W21]>, DwarfRegAlias<W21>;
112 def X22 : AArch64Reg<22, "x22", [W22]>, DwarfRegAlias<W22>;
113 def X23 : AArch64Reg<23, "x23", [W23]>, DwarfRegAlias<W23>;
114 def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>;
115 def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
116 def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
117 def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
118 def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
119 def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
120 def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
121 def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
122 def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
126 def NZCV : AArch64Reg<0, "nzcv">;
130 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
134 def GPR64common : RegisterClass<"AArch64", [i64], 64,
140 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
144 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
150 def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {
154 def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {
159 def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
160 def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
162 def GPR64spPlus0Operand : AsmOperandClass {
168 def GPR64sp0 : RegisterOperand<GPR64sp> {
174 def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>;
175 def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>;
180 def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21,
191 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
192 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
193 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
194 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
195 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
196 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">;
197 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
198 def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">;
199 def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">;
200 def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">;
201 def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;
202 def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;
205 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
216 def B0 : AArch64Reg<0, "b0">, DwarfRegNum<[64]>;
217 def B1 : AArch64Reg<1, "b1">, DwarfRegNum<[65]>;
218 def B2 : AArch64Reg<2, "b2">, DwarfRegNum<[66]>;
219 def B3 : AArch64Reg<3, "b3">, DwarfRegNum<[67]>;
220 def B4 : AArch64Reg<4, "b4">, DwarfRegNum<[68]>;
221 def B5 : AArch64Reg<5, "b5">, DwarfRegNum<[69]>;
222 def B6 : AArch64Reg<6, "b6">, DwarfRegNum<[70]>;
223 def B7 : AArch64Reg<7, "b7">, DwarfRegNum<[71]>;
224 def B8 : AArch64Reg<8, "b8">, DwarfRegNum<[72]>;
225 def B9 : AArch64Reg<9, "b9">, DwarfRegNum<[73]>;
226 def B10 : AArch64Reg<10, "b10">, DwarfRegNum<[74]>;
227 def B11 : AArch64Reg<11, "b11">, DwarfRegNum<[75]>;
228 def B12 : AArch64Reg<12, "b12">, DwarfRegNum<[76]>;
229 def B13 : AArch64Reg<13, "b13">, DwarfRegNum<[77]>;
230 def B14 : AArch64Reg<14, "b14">, DwarfRegNum<[78]>;
231 def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>;
232 def B16 : AArch64Reg<16, "b16">, DwarfRegNum<[80]>;
233 def B17 : AArch64Reg<17, "b17">, DwarfRegNum<[81]>;
234 def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>;
235 def B19 : AArch64Reg<19, "b19">, DwarfRegNum<[83]>;
236 def B20 : AArch64Reg<20, "b20">, DwarfRegNum<[84]>;
237 def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>;
238 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
239 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>;
240 def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>;
241 def B25 : AArch64Reg<25, "b25">, DwarfRegNum<[89]>;
242 def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>;
243 def B27 : AArch64Reg<27, "b27">, DwarfRegNum<[91]>;
244 def B28 : AArch64Reg<28, "b28">, DwarfRegNum<[92]>;
245 def B29 : AArch64Reg<29, "b29">, DwarfRegNum<[93]>;
246 def B30 : AArch64Reg<30, "b30">, DwarfRegNum<[94]>;
247 def B31 : AArch64Reg<31, "b31">, DwarfRegNum<[95]>;
250 def H0 : AArch64Reg<0, "h0", [B0]>, DwarfRegAlias<B0>;
251 def H1 : AArch64Reg<1, "h1", [B1]>, DwarfRegAlias<B1>;
252 def H2 : AArch64Reg<2, "h2", [B2]>, DwarfRegAlias<B2>;
253 def H3 : AArch64Reg<3, "h3", [B3]>, DwarfRegAlias<B3>;
254 def H4 : AArch64Reg<4, "h4", [B4]>, DwarfRegAlias<B4>;
255 def H5 : AArch64Reg<5, "h5", [B5]>, DwarfRegAlias<B5>;
256 def H6 : AArch64Reg<6, "h6", [B6]>, DwarfRegAlias<B6>;
257 def H7 : AArch64Reg<7, "h7", [B7]>, DwarfRegAlias<B7>;
258 def H8 : AArch64Reg<8, "h8", [B8]>, DwarfRegAlias<B8>;
259 def H9 : AArch64Reg<9, "h9", [B9]>, DwarfRegAlias<B9>;
260 def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>;
261 def H11 : AArch64Reg<11, "h11", [B11]>, DwarfRegAlias<B11>;
262 def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>;
263 def H13 : AArch64Reg<13, "h13", [B13]>, DwarfRegAlias<B13>;
264 def H14 : AArch64Reg<14, "h14", [B14]>, DwarfRegAlias<B14>;
265 def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
266 def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;
267 def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>;
268 def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
269 def H19 : AArch64Reg<19, "h19", [B19]>, DwarfRegAlias<B19>;
270 def H20 : AArch64Reg<20, "h20", [B20]>, DwarfRegAlias<B20>;
271 def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
272 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
273 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>;
274 def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
275 def H25 : AArch64Reg<25, "h25", [B25]>, DwarfRegAlias<B25>;
276 def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
277 def H27 : AArch64Reg<27, "h27", [B27]>, DwarfRegAlias<B27>;
278 def H28 : AArch64Reg<28, "h28", [B28]>, DwarfRegAlias<B28>;
279 def H29 : AArch64Reg<29, "h29", [B29]>, DwarfRegAlias<B29>;
280 def H30 : AArch64Reg<30, "h30", [B30]>, DwarfRegAlias<B30>;
281 def H31 : AArch64Reg<31, "h31", [B31]>, DwarfRegAlias<B31>;
285 def S0 : AArch64Reg<0, "s0", [H0]>, DwarfRegAlias<B0>;
286 def S1 : AArch64Reg<1, "s1", [H1]>, DwarfRegAlias<B1>;
287 def S2 : AArch64Reg<2, "s2", [H2]>, DwarfRegAlias<B2>;
288 def S3 : AArch64Reg<3, "s3", [H3]>, DwarfRegAlias<B3>;
289 def S4 : AArch64Reg<4, "s4", [H4]>, DwarfRegAlias<B4>;
290 def S5 : AArch64Reg<5, "s5", [H5]>, DwarfRegAlias<B5>;
291 def S6 : AArch64Reg<6, "s6", [H6]>, DwarfRegAlias<B6>;
292 def S7 : AArch64Reg<7, "s7", [H7]>, DwarfRegAlias<B7>;
293 def S8 : AArch64Reg<8, "s8", [H8]>, DwarfRegAlias<B8>;
294 def S9 : AArch64Reg<9, "s9", [H9]>, DwarfRegAlias<B9>;
295 def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
296 def S11 : AArch64Reg<11, "s11", [H11]>, DwarfRegAlias<B11>;
297 def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;
298 def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
299 def S14 : AArch64Reg<14, "s14", [H14]>, DwarfRegAlias<B14>;
300 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
301 def S16 : AArch64Reg<16, "s16", [H16]>, DwarfRegAlias<B16>;
302 def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
303 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
304 def S19 : AArch64Reg<19, "s19", [H19]>, DwarfRegAlias<B19>;
305 def S20 : AArch64Reg<20, "s20", [H20]>, DwarfRegAlias<B20>;
306 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
307 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
308 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>;
309 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
310 def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
311 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
312 def S27 : AArch64Reg<27, "s27", [H27]>, DwarfRegAlias<B27>;
313 def S28 : AArch64Reg<28, "s28", [H28]>, DwarfRegAlias<B28>;
314 def S29 : AArch64Reg<29, "s29", [H29]>, DwarfRegAlias<B29>;
315 def S30 : AArch64Reg<30, "s30", [H30]>, DwarfRegAlias<B30>;
316 def S31 : AArch64Reg<31, "s31", [H31]>, DwarfRegAlias<B31>;
320 def D0 : AArch64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias<B0>;
321 def D1 : AArch64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias<B1>;
322 def D2 : AArch64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias<B2>;
323 def D3 : AArch64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias<B3>;
324 def D4 : AArch64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias<B4>;
325 def D5 : AArch64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias<B5>;
326 def D6 : AArch64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias<B6>;
327 def D7 : AArch64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias<B7>;
328 def D8 : AArch64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias<B8>;
329 def D9 : AArch64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias<B9>;
330 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
331 def D11 : AArch64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias<B11>;
332 def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;
333 def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
334 def D14 : AArch64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias<B14>;
335 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
336 def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>;
337 def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
338 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
339 def D19 : AArch64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias<B19>;
340 def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>;
341 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
342 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
343 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
344 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
345 def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
346 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
347 def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
348 def D28 : AArch64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias<B28>;
349 def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>;
350 def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>;
351 def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
355 def Q0 : AArch64Reg<0, "q0", [D0], ["v0", ""]>, DwarfRegAlias<B0>;
356 def Q1 : AArch64Reg<1, "q1", [D1], ["v1", ""]>, DwarfRegAlias<B1>;
357 def Q2 : AArch64Reg<2, "q2", [D2], ["v2", ""]>, DwarfRegAlias<B2>;
358 def Q3 : AArch64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias<B3>;
359 def Q4 : AArch64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias<B4>;
360 def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>;
361 def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>;
362 def Q7 : AArch64Reg<7, "q7", [D7], ["v7", ""]>, DwarfRegAlias<B7>;
363 def Q8 : AArch64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias<B8>;
364 def Q9 : AArch64Reg<9, "q9", [D9], ["v9", ""]>, DwarfRegAlias<B9>;
365 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
366 def Q11 : AArch64Reg<11, "q11", [D11], ["v11", ""]>, DwarfRegAlias<B11>;
367 def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
368 def Q13 : AArch64Reg<13, "q13", [D13], ["v13", ""]>, DwarfRegAlias<B13>;
369 def Q14 : AArch64Reg<14, "q14", [D14], ["v14", ""]>, DwarfRegAlias<B14>;
370 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
371 def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>;
372 def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>;
373 def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
374 def Q19 : AArch64Reg<19, "q19", [D19], ["v19", ""]>, DwarfRegAlias<B19>;
375 def Q20 : AArch64Reg<20, "q20", [D20], ["v20", ""]>, DwarfRegAlias<B20>;
376 def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
377 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
378 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
379 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
380 def Q25 : AArch64Reg<25, "q25", [D25], ["v25", ""]>, DwarfRegAlias<B25>;
381 def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
382 def Q27 : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>;
383 def Q28 : AArch64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias<B28>;
384 def Q29 : AArch64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias<B29>;
385 def Q30 : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>;
386 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
389 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
392 def FPR16 : RegisterClass<"AArch64", [f16], 16, (sequence "H%u", 0, 31)> {
395 def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
396 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
402 def FPR128 : RegisterClass<"AArch64",
409 def FPR128_lo : RegisterClass<"AArch64",
414 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
415 def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2],
418 def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],
421 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
424 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
427 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
432 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
433 def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2],
436 def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3],
439 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
442 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
445 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
452 def VectorReg64AsmOperand : AsmOperandClass {
456 def VectorReg128AsmOperand : AsmOperandClass {
461 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
465 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
469 def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; }
470 def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
489 def _64AsmOperand : AsmOperandClass {
495 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
499 def _128AsmOperand : AsmOperandClass {
505 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
512 def _8bAsmOperand : TypedVecListAsmOperand<count, 64, 8, "b">;
513 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
518 def _4hAsmOperand : TypedVecListAsmOperand<count, 64, 4, "h">;
519 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
524 def _2sAsmOperand : TypedVecListAsmOperand<count, 64, 2, "s">;
525 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
530 def _1dAsmOperand : TypedVecListAsmOperand<count, 64, 1, "d">;
531 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
538 def _16bAsmOperand : TypedVecListAsmOperand<count, 128, 16, "b">;
539 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
544 def _8hAsmOperand : TypedVecListAsmOperand<count, 128, 8, "h">;
545 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
550 def _4sAsmOperand : TypedVecListAsmOperand<count, 128, 4, "s">;
551 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
556 def _2dAsmOperand : TypedVecListAsmOperand<count, 128, 2, "d">;
557 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
562 def _bAsmOperand : TypedVecListAsmOperand<count, 128, 0, "b">;
563 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
568 def _hAsmOperand : TypedVecListAsmOperand<count, 128, 0, "h">;
569 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
574 def _sAsmOperand : TypedVecListAsmOperand<count, 128, 0, "s">;
575 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
580 def _dAsmOperand : TypedVecListAsmOperand<count, 128, 0, "d">;
581 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
595 def FPR16Op : RegisterOperand<FPR16, "printOperand">;
596 def FPR32Op : RegisterOperand<FPR32, "printOperand">;
597 def FPR64Op : RegisterOperand<FPR64, "printOperand">;
598 def FPR128Op : RegisterOperand<FPR128, "printOperand">;
605 def WSeqPairs : RegisterTuples<[sube32, subo32],
607 def XSeqPairs : RegisterTuples<[sube64, subo64],
610 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
614 def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
621 def WSeqPairsAsmOperandClass : AsmOperandClass { let Name = "WSeqPair"; }
622 def XSeqPairsAsmOperandClass : AsmOperandClass { let Name = "XSeqPair"; }
625 def WSeqPairClassOperand :
629 def XSeqPairClassOperand :