Lines Matching refs:def
24 def CortexA57Model : SchedMachineModel {
41 def A57UnitB : ProcResource<1>; // Type B micro-ops
42 def A57UnitI : ProcResource<2>; // Type I micro-ops
43 def A57UnitM : ProcResource<1>; // Type M micro-ops
44 def A57UnitL : ProcResource<1>; // Type L micro-ops
45 def A57UnitS : ProcResource<1>; // Type S micro-ops
46 def A57UnitX : ProcResource<1>; // Type X micro-ops
47 def A57UnitW : ProcResource<1>; // Type W micro-ops
49 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
71 def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
72 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
73 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
74 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
75 def : SchedAlias<WriteExtr, A57Write_1cyc_1I>;
76 def : SchedAlias<WriteIS, A57Write_1cyc_1I>;
77 def : SchedAlias<WriteID32, A57Write_19cyc_1M>;
78 def : SchedAlias<WriteID64, A57Write_35cyc_1M>;
79 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
80 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
81 def : SchedAlias<WriteBr, A57Write_1cyc_1B>;
82 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
83 def : SchedAlias<WriteLD, A57Write_4cyc_1L>;
84 def : SchedAlias<WriteST, A57Write_1cyc_1S>;
85 def : SchedAlias<WriteSTP, A57Write_1cyc_1S>;
86 def : SchedAlias<WriteAdr, A57Write_1cyc_1I>;
87 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
88 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
89 def : SchedAlias<WriteF, A57Write_3cyc_1V>;
90 def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>;
91 def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>;
92 def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>;
93 def : SchedAlias<WriteFImm, A57Write_3cyc_1V>;
94 def : SchedAlias<WriteFMul, A57Write_5cyc_1V>;
95 def : SchedAlias<WriteFDiv, A57Write_18cyc_1X>;
96 def : SchedAlias<WriteV, A57Write_3cyc_1V>;
97 def : SchedAlias<WriteVLD, A57Write_5cyc_1L>;
98 def : SchedAlias<WriteVST, A57Write_1cyc_1S>;
100 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
102 def : WriteRes<WriteSys, []> { let Latency = 1; }
103 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
104 def : WriteRes<WriteHint, []> { let Latency = 1; }
106 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
109 def : ReadAdvance<ReadI, 0>;
110 def : ReadAdvance<ReadISReg, 0>;
111 def : ReadAdvance<ReadIEReg, 0>;
112 def : ReadAdvance<ReadIM, 0>;
113 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
114 def : ReadAdvance<ReadID, 0>;
115 def : ReadAdvance<ReadExtrHi, 0>;
116 def : ReadAdvance<ReadAdrBase, 0>;
117 def : ReadAdvance<ReadVLD, 0>;
128 def : InstRW<[WriteI], (instrs COPY)>;
134 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
135 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
141 def A57WriteISReg : SchedWriteVariant<[
144 def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
151 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
157 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
158 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
159 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
165 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES")>;
166 def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;
167 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;
168 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;
169 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;
170 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
171 def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>;
177 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>;
178 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
179 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>;
180 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>;
182 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>;
183 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
184 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>;
185 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>;
186 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
187 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
189 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
190 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
191 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
192 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
193 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
194 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
195 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
196 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
197 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
198 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
199 def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
200 def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
201 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
202 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
203 def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
204 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
206 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>;
207 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
208 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>;
209 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>;
210 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>;
211 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>;
213 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>;
214 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>;
215 def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>;
216 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>;
217 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
218 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
220 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>;
221 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
222 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>;
223 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
224 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>;
225 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>;
227 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>;
228 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
229 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>;
230 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>;
231 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>;
232 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>;
234 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>;
235 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>;
236 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>;
237 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>;
238 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>;
239 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>;
240 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>;
241 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
243 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>;
244 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
245 def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>;
246 def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
247 def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>;
248 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
250 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>;
251 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
252 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>;
253 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>;
254 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>;
255 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
257 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>;
258 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>;
259 def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>;
260 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>;
261 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>;
262 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>;
263 def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>;
264 def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
266 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>;
267 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
268 def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>;
269 def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
270 def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>;
271 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
276 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>;
277 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>;
278 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>;
279 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
281 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
282 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
283 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
284 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
285 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
286 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
287 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
288 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
289 def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
290 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
291 def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
292 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
293 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
294 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
295 def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
296 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
298 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>;
299 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
300 def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>;
301 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
303 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
304 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
305 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>;
306 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
307 def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>;
308 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>;
310 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>;
311 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>;
312 def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>;
313 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
314 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>;
315 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
317 def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
318 def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
319 def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>;
320 def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
321 def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>;
322 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
324 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>;
325 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>;
326 def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>;
327 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
328 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>;
329 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>;
331 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>;
332 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
333 def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>;
334 def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
335 def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>;
336 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
350 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
352 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
354 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>;
357 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
359 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
361 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
364 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
366 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
368 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
373 def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
376 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
378 def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
382 def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
383 def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>;
384 def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>;
387 def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>;
388 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
389 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
393 def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
394 def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>;
395 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>;
396 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
399 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>;
400 def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
404 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
410 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
425 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
427 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
430 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
432 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
435 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|…
437 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f…
440 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
442 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
444 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i6…
447 def : InstRW<[A57Write_18cyc_1X], (instregex "FDIVv2f32")>;
449 def : InstRW<[A57Write_36cyc_2X], (instregex "FDIVv4f32")>;
451 def : InstRW<[A57Write_64cyc_2X], (instregex "FDIVv2f64")>;
455 def : InstRW<[A57Write_18cyc_1X], (instregex "FSQRTv2f32")>;
457 def : InstRW<[A57Write_36cyc_2X], (instregex "FSQRTv4f32")>;
459 def : InstRW<[A57Write_64cyc_2X], (instregex "FSQRTv2f64")>;
462 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
464 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
466 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
468 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
470 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
473 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
475 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
479 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
480 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }
481 def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>;
482 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
483 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
486 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
488 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
501 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>;
504 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
505 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
508 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
511 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
513 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
516 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
518 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
521 def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
522 def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
523 def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
524 def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
526 def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
527 def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
528 def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
529 def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
532 def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>;
535 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>;
538 def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
544 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
546 def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
547 def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>;
548 def A57ReadFPM : SchedReadAdvance<0>;
549 def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rr…
551 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?"…
552 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>;
554 def : InstRW<[A57Write_32cyc_1X], (instrs FDIVDrr)>;
555 def : InstRW<[A57Write_18cyc_1X], (instrs FDIVSrr)>;
557 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>;
559 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
561 def : InstRW<[A57Write_32cyc_1X], (instrs FSQRTDr)>;
562 def : InstRW<[A57Write_18cyc_1X], (instrs FSQRTSr)>;
564 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>;
565 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>;
566 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>;
567 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>;
568 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>;
569 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>;
570 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>;
571 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>;
572 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>;
573 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>;
574 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
575 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
576 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>;
577 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>;
578 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>;
579 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
580 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>;
581 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>;
582 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>;
583 def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>;
584 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>;
585 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
586 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>;
587 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>;
588 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>;
589 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>;
590 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>;
591 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>;
592 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
593 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>;
594 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>;
595 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>;
596 def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>;
597 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>;
598 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
599 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>;
600 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>;
601 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>;
602 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>;
603 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>;
604 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>;
605 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>;
606 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>;
607 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>;
608 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
609 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>;
610 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>;
611 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>;
612 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>;
613 def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>;
614 def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>;
615 def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>;
616 def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>;
617 def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>;
619 def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>;
620 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>;
621 def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>;
622 def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>;
623 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>;
624 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>;
625 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>;
626 def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>;
627 def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>;
628 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>;
629 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>;
630 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>;
631 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>;
632 def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>;
633 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>;
634 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>;
635 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>;
636 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>;
637 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>;
638 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>;
639 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>;
640 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>;
641 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>;
642 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>;
643 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>;
644 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>;
645 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>;
646 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>;
647 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>;
648 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>;
649 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>;
650 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>;
651 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>;
652 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>;
653 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>;
654 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>;
655 def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>;
656 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>;
657 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>;
658 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>;
659 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
660 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
661 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
662 def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;