Lines Matching refs:WriteRes

54 // by a WriteRes later on.
217 def : WriteRes<WriteBr,      [VulcanI2]> { let Latency = 1; }
219 def : WriteRes<WriteSys,     []> { let Latency = 1; }
220 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
221 def : WriteRes<WriteHint,    []> { let Latency = 1; }
223 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
228 def : WriteRes<WriteBrReg,   [VulcanI2]> { let Latency = 1; }
239 def : WriteRes<WriteI,       [VulcanI012]> { let Latency = 1; }
243 def : WriteRes<WriteISReg,   [VulcanI012]> {
248 def : WriteRes<WriteIEReg,   [VulcanI012]> {
254 def : WriteRes<WriteImm,     [VulcanI012]> { let Latency = 1; }
257 def : WriteRes<WriteIS,      [VulcanI012]> { let Latency = 1; }
265 def : WriteRes<WriteID32,    [VulcanI1]> {
272 def : WriteRes<WriteID64,    [VulcanI1]> {
278 def : WriteRes<WriteIM32,    [VulcanI012]> { let Latency = 5; }
281 def : WriteRes<WriteIM64,    [VulcanI012]> { let Latency = 5; }
284 def : WriteRes<WriteExtr,    [VulcanI012]> { let Latency = 1; }
306 def : WriteRes<WriteLD,      [VulcanLS01]> { let Latency = 4; }
312 def : WriteRes<WriteAdr,     [VulcanI012]> { let Latency = 1; }
335 def : WriteRes<WriteLDHi,    []> {
353 def : WriteRes<WriteST,      [VulcanLS01, VulcanSD]> {
370 def : WriteRes<WriteSTIdx, [VulcanLS01, VulcanSD, VulcanI012]> {
377 def : WriteRes<WriteSTP,     [VulcanLS01, VulcanSD]> {
395 def : WriteRes<WriteF,       [VulcanF01]> { let Latency = 5; }
401 def : WriteRes<WriteFCmp,    [VulcanF01]> { let Latency = 5; }
405 def : WriteRes<WriteFDiv,    [VulcanF01]> {
416 def : WriteRes<WriteFMul, [VulcanF01]> { let Latency = 6; }
432 def : WriteRes<WriteFCvt, [VulcanF01]> { let Latency = 7; }
436 def : WriteRes<WriteFImm, [VulcanF01]> { let Latency = 4; }
440 def : WriteRes<WriteFCopy, [VulcanF01]> { let Latency = 4; }
476 def : WriteRes<WriteV, [VulcanF01]> { let Latency = 7; }