656   return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);  in LowerReturn()
791       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);  in LowerConstantInitializer()
797     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);  in LowerConstantInitializer()
815       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);  in LowerConstantInitializer()
821     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);  in LowerConstantInitializer()
856     return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(G), ConstPtrVT, GA);  in LowerGlobalAddress()
926       return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
930       return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),  in LowerINTRINSIC_WO_CHAIN()
934       return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
940       return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,  in LowerINTRINSIC_WO_CHAIN()
946       return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1));  in LowerINTRINSIC_WO_CHAIN()
981       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
982     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1000       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1001     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1006       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1007     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1018       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);  in CombineFMinMaxLegacy()
1019     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);  in CombineFMinMaxLegacy()
1031   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);  in split64BitValue()
1036   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);  in split64BitValue()
1037   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);  in split64BitValue()
1045   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);  in getLoHalf64()
1047   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);  in getLoHalf64()
1053   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);  in getHiHalf64()
1055   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);  in getHiHalf64()
1095   SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,  in SplitVectorLoad()
1106     DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),  in SplitVectorLoad()
1107     DAG.getNode(ISD::TokenFactor, SL, MVT::Other,  in SplitVectorLoad()
1144     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,  in MergeVectorStore()
1147     Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg  in MergeVectorStore()
1150     Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);  in MergeVectorStore()
1155       PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);  in MergeVectorStore()
1199   SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,  in SplitVectorStore()
1225   return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);  in SplitVectorStore()
1261     jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);  in LowerDIVREM24()
1264     jq = DAG.getNode(ISD::SRA, DL, VT, jq,  in LowerDIVREM24()
1268     jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));  in LowerDIVREM24()
1278   SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);  in LowerDIVREM24()
1281   SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);  in LowerDIVREM24()
1283   SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,  in LowerDIVREM24()
1284                            fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));  in LowerDIVREM24()
1287   fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);  in LowerDIVREM24()
1290   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);  in LowerDIVREM24()
1293   SDValue fr = DAG.getNode(ISD::FMAD, DL, FltVT, fqneg, fb, fa);  in LowerDIVREM24()
1296   SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);  in LowerDIVREM24()
1299   fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);  in LowerDIVREM24()
1302   fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);  in LowerDIVREM24()
1310   jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));  in LowerDIVREM24()
1313   SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);  in LowerDIVREM24()
1316   SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);  in LowerDIVREM24()
1317   Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);  in LowerDIVREM24()
1323     Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);  in LowerDIVREM24()
1324     Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);  in LowerDIVREM24()
1327     Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);  in LowerDIVREM24()
1328     Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);  in LowerDIVREM24()
1348   SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);  in LowerUDIVREM64()
1349   SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);  in LowerUDIVREM64()
1352   SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);  in LowerUDIVREM64()
1353   SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);  in LowerUDIVREM64()
1359     SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),  in LowerUDIVREM64()
1365     Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));  in LowerUDIVREM64()
1366     Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));  in LowerUDIVREM64()
1371   SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);  in LowerUDIVREM64()
1372   SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);  in LowerUDIVREM64()
1376   REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);  in LowerUDIVREM64()
1387     SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);  in LowerUDIVREM64()
1388     HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);  in LowerUDIVREM64()
1389     HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);  in LowerUDIVREM64()
1392     REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));  in LowerUDIVREM64()
1394     REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);  in LowerUDIVREM64()
1399     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);  in LowerUDIVREM64()
1402     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);  in LowerUDIVREM64()
1407   DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);  in LowerUDIVREM64()
1433   SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);  in LowerUDIVREM()
1436   SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);  in LowerUDIVREM()
1439   SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);  in LowerUDIVREM()
1442   SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),  in LowerUDIVREM()
1451   SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);  in LowerUDIVREM()
1454   SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);  in LowerUDIVREM()
1457   SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);  in LowerUDIVREM()
1464   SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);  in LowerUDIVREM()
1467   SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);  in LowerUDIVREM()
1470   SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);  in LowerUDIVREM()
1484   SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,  in LowerUDIVREM()
1490   SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,  in LowerUDIVREM()
1494   SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,  in LowerUDIVREM()
1508   SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);  in LowerUDIVREM()
1511   SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);  in LowerUDIVREM()
1549     SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);  in LowerSDIVREM()
1550     SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);  in LowerSDIVREM()
1551     SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),  in LowerSDIVREM()
1554       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),  in LowerSDIVREM()
1555       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))  in LowerSDIVREM()
1562   SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);  in LowerSDIVREM()
1565   LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);  in LowerSDIVREM()
1566   RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);  in LowerSDIVREM()
1568   LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);  in LowerSDIVREM()
1569   RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);  in LowerSDIVREM()
1571   SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);  in LowerSDIVREM()
1574   Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);  in LowerSDIVREM()
1575   Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);  in LowerSDIVREM()
1577   Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);  in LowerSDIVREM()
1578   Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);  in LowerSDIVREM()
1596   SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);  in LowerFREM()
1597   SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);  in LowerFREM()
1598   SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);  in LowerFREM()
1600   return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);  in LowerFREM()
1611   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);  in LowerFCEIL()
1621   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);  in LowerFCEIL()
1623   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);  in LowerFCEIL()
1625   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);  in LowerFCEIL()
1633   SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,  in extractF64Exponent()
1637   SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,  in extractF64Exponent()
1652   SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);  in LowerFTRUNC()
1656   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);  in LowerFTRUNC()
1664   SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);  in LowerFTRUNC()
1668   SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);  in LowerFTRUNC()
1670   SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);  in LowerFTRUNC()
1674   SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);  in LowerFTRUNC()
1676   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);  in LowerFTRUNC()
1686   SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);  in LowerFTRUNC()
1687   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);  in LowerFTRUNC()
1689   return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);  in LowerFTRUNC()
1700   SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);  in LowerFRINT()
1704   SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);  in LowerFRINT()
1705   SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);  in LowerFRINT()
1707   SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);  in LowerFRINT()
1723   return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));  in LowerFNEARBYINT()
1731   SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);  in LowerFROUND32()
1735   SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);  in LowerFROUND32()
1737   SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);  in LowerFROUND32()
1743   SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);  in LowerFROUND32()
1750   SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);  in LowerFROUND32()
1752   return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);  in LowerFROUND32()
1759   SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);  in LowerFROUND64()
1768   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);  in LowerFROUND64()
1770   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);  in LowerFROUND64()
1777   SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);  in LowerFROUND64()
1778   SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,  in LowerFROUND64()
1783   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);  in LowerFROUND64()
1788   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,  in LowerFROUND64()
1790   SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);  in LowerFROUND64()
1792   K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));  in LowerFROUND64()
1793   K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);  in LowerFROUND64()
1799   SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,  in LowerFROUND64()
1804   SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);  in LowerFROUND64()
1806   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);  in LowerFROUND64()
1807   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);  in LowerFROUND64()
1832   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);  in LowerFFLOOR()
1842   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);  in LowerFFLOOR()
1844   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);  in LowerFFLOOR()
1846   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);  in LowerFFLOOR()
1855     return DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Src);  in LowerCTLZ()
1857   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);  in LowerCTLZ()
1862   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);  in LowerCTLZ()
1863   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);  in LowerCTLZ()
1870   SDValue CtlzLo = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Lo);  in LowerCTLZ()
1871   SDValue CtlzHi = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi);  in LowerCTLZ()
1874   SDValue Add = DAG.getNode(ISD::ADD, SL, MVT::i32, CtlzLo, Bits32);  in LowerCTLZ()
1877   SDValue NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0, Add, CtlzHi);  in LowerCTLZ()
1885     SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0, Hi0);  in LowerCTLZ()
1896     NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32,  in LowerCTLZ()
1900   return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewCtlz);  in LowerCTLZ()
1931     S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);  in LowerINT_TO_FP32()
1933     SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);  in LowerINT_TO_FP32()
1934     L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);  in LowerINT_TO_FP32()
1943   SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);  in LowerINT_TO_FP32()
1944   LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);  in LowerINT_TO_FP32()
1949     DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),  in LowerINT_TO_FP32()
1952   SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,  in LowerINT_TO_FP32()
1953     DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),  in LowerINT_TO_FP32()
1956   SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,  in LowerINT_TO_FP32()
1959   SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,  in LowerINT_TO_FP32()
1962   SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,  in LowerINT_TO_FP32()
1963     DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),  in LowerINT_TO_FP32()
1964     DAG.getNode(ISD::TRUNCATE, SL, MVT::i32,  UShl));  in LowerINT_TO_FP32()
1972   SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);  in LowerINT_TO_FP32()
1978   R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);  in LowerINT_TO_FP32()
1979   R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);  in LowerINT_TO_FP32()
1984   SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);  in LowerINT_TO_FP32()
1993   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);  in LowerINT_TO_FP64()
1995   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,  in LowerINT_TO_FP64()
1997   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,  in LowerINT_TO_FP64()
2000   SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,  in LowerINT_TO_FP64()
2003   SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);  in LowerINT_TO_FP64()
2005   SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,  in LowerINT_TO_FP64()
2008   return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);  in LowerINT_TO_FP64()
2047   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);  in LowerFP64_TO_INT()
2054   SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);  in LowerFP64_TO_INT()
2056   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);  in LowerFP64_TO_INT()
2059   SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);  in LowerFP64_TO_INT()
2061   SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,  in LowerFP64_TO_INT()
2063   SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);  in LowerFP64_TO_INT()
2067   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);  in LowerFP64_TO_INT()
2109     Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);  in LowerSIGN_EXTEND_INREG()
2234   SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);  in performLoadCombine()
2280   SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);  in performStoreCombine()
2282     SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);  in performStoreCombine()
2320   SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS);  in performAndCombine()
2321   SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS);  in performAndCombine()
2325   DCI.AddToWorklist(Lo.getNode());  in performAndCombine()
2326   DCI.AddToWorklist(Hi.getNode());  in performAndCombine()
2329   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);  in performAndCombine()
2357   SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);  in performShlCombine()
2358   SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);  in performShlCombine()
2363   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);  in performShlCombine()
2382     SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,  in performSraCombine()
2386     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);  in performSraCombine()
2392     SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,  in performSraCombine()
2395     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);  in performSraCombine()
2424   SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));  in performSrlCombine()
2425   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,  in performSrlCombine()
2429   SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);  in performSrlCombine()
2433   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);  in performSrlCombine()
2453     Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);  in performMulCombine()
2457     Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);  in performMulCombine()
2489     Op = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Op);  in getFFBH_U32()
2491   SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Op);  in getFFBH_U32()
2493     FFBH = DAG.getNode(ISD::TRUNCATE, SL, VT, FFBH);  in getFFBH_U32()
2583       return DAG.getNode(ISD::BUILD_VECTOR, SL, DestVT,  in PerformDAGCombine()
2592       SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,  in PerformDAGCombine()
2596       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);  in PerformDAGCombine()
2674         return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,  in PerformDAGCombine()
2699       return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,  in PerformDAGCombine()
2886     return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);  in getRsqrtEstimate()
2908     return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);  in getRecipEstimate()