71     NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))  in copyPhysReg()
148   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;  in isLDSNoRetInstr()
152   return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;  in isLDSRetInstr()
259   return getOperandIdx(Opcode, OpTable[SrcNum]);  in getSrcIdx()
278     if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {  in getSelIdx()
279       return getOperandIdx(Opcode, Row[1]);  in getSelIdx()
303           MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));  in getSrcs()
307             MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));  in getSrcs()
323     int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);  in getSrcs()
330           MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));  in getSrcs()
336           MI.getOperand(getOperandIdx(MI.getOpcode(), AMDGPU::OpName::literal));  in getSrcs()
557     unsigned Op = getOperandIdx(IG[i]->getOpcode(),  in fitsReadPortLimitations()
1000     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))  in PredicateInstruction()
1002     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))  in PredicateInstruction()
1004     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))  in PredicateInstruction()
1006     MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))  in PredicateInstruction()
1350       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));  in buildSlotOfVectorInstruction()
1352       getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));  in buildSlotOfVectorInstruction()
1372   MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),  in buildSlotOfVectorInstruction()
1374   MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))  in buildSlotOfVectorInstruction()
1379         getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));  in buildSlotOfVectorInstruction()
1403 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {  in getOperandIdx()  function in R600InstrInfo
1404   return getOperandIdx(MI.getOpcode(), Op);  in getOperandIdx()
1407 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {  in getOperandIdx()  function in R600InstrInfo
1413   int Idx = getOperandIdx(MI, Op);  in setImmOperand()
1439       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::clamp);  in getFlagOp()
1442       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::write);  in getFlagOp()
1446       FlagIndex = getOperandIdx(MI, AMDGPU::OpName::last);  in getFlagOp()
1451         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_neg);  in getFlagOp()
1454         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_neg);  in getFlagOp()
1457         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src2_neg);  in getFlagOp()
1468         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_abs);  in getFlagOp()
1471         FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_abs);  in getFlagOp()