44   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
50   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
86   unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
89   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
106   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
120   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
124   unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
129                            MachineBasicBlock::iterator MI, unsigned SrcReg,
135                             MachineBasicBlock::iterator MI, unsigned DestReg,
139   bool expandPostRAPseudo(MachineInstr &MI) const override;
147   int commuteOpcode(const MachineInstr &MI) const;
149   bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
176                                       MachineInstr &MI,
179   bool isSchedulingBoundary(const MachineInstr &MI,
183   static bool isSALU(const MachineInstr &MI) {  in isSALU()  argument
184     return MI.getDesc().TSFlags & SIInstrFlags::SALU;  in isSALU()
191   static bool isVALU(const MachineInstr &MI) {  in isVALU()  argument
192     return MI.getDesc().TSFlags & SIInstrFlags::VALU;  in isVALU()
199   static bool isVMEM(const MachineInstr &MI) {  in isVMEM()  argument
200     return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);  in isVMEM()
207   static bool isSOP1(const MachineInstr &MI) {  in isSOP1()  argument
208     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;  in isSOP1()
215   static bool isSOP2(const MachineInstr &MI) {  in isSOP2()  argument
216     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;  in isSOP2()
223   static bool isSOPC(const MachineInstr &MI) {  in isSOPC()  argument
224     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;  in isSOPC()
231   static bool isSOPK(const MachineInstr &MI) {  in isSOPK()  argument
232     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;  in isSOPK()
239   static bool isSOPP(const MachineInstr &MI) {  in isSOPP()  argument
240     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;  in isSOPP()
247   static bool isVOP1(const MachineInstr &MI) {  in isVOP1()  argument
248     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;  in isVOP1()
255   static bool isVOP2(const MachineInstr &MI) {  in isVOP2()  argument
256     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;  in isVOP2()
263   static bool isVOP3(const MachineInstr &MI) {  in isVOP3()  argument
264     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;  in isVOP3()
271   static bool isVOPC(const MachineInstr &MI) {  in isVOPC()  argument
272     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;  in isVOPC()
279   static bool isMUBUF(const MachineInstr &MI) {  in isMUBUF()  argument
280     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;  in isMUBUF()
287   static bool isMTBUF(const MachineInstr &MI) {  in isMTBUF()  argument
288     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;  in isMTBUF()
295   static bool isSMRD(const MachineInstr &MI) {  in isSMRD()  argument
296     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;  in isSMRD()
303   static bool isDS(const MachineInstr &MI) {  in isDS()  argument
304     return MI.getDesc().TSFlags & SIInstrFlags::DS;  in isDS()
311   static bool isMIMG(const MachineInstr &MI) {  in isMIMG()  argument
312     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;  in isMIMG()
319   static bool isGather4(const MachineInstr &MI) {  in isGather4()  argument
320     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;  in isGather4()
327   static bool isFLAT(const MachineInstr &MI) {  in isFLAT()  argument
328     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;  in isFLAT()
335   static bool isWQM(const MachineInstr &MI) {  in isWQM()  argument
336     return MI.getDesc().TSFlags & SIInstrFlags::WQM;  in isWQM()
343   static bool isVGPRSpill(const MachineInstr &MI) {  in isVGPRSpill()  argument
344     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;  in isVGPRSpill()
351   static bool isDPP(const MachineInstr &MI) {  in isDPP()  argument
352     return MI.getDesc().TSFlags & SIInstrFlags::DPP;  in isDPP()
359   static bool isScalarUnit(const MachineInstr &MI) {  in isScalarUnit()  argument
360     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);  in isScalarUnit()
363   static bool usesVM_CNT(const MachineInstr &MI) {  in usesVM_CNT()  argument
364     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;  in usesVM_CNT()
367   bool isVGPRCopy(const MachineInstr &MI) const {  in isVGPRCopy()  argument
368     assert(MI.isCopy());  in isVGPRCopy()
369     unsigned Dest = MI.getOperand(0).getReg();  in isVGPRCopy()
370     const MachineFunction &MF = *MI.getParent()->getParent();  in isVGPRCopy()
379   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
395   bool hasModifiersSet(const MachineInstr &MI,
398   bool verifyInstruction(const MachineInstr &MI,
401   static unsigned getVALUOp(const MachineInstr &MI);
403   bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
410   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
429   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {  in getOpSize()  argument
430     return getOpRegClass(MI, OpNo)->getSize();  in getOpSize()
435   bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
446   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
450   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
468   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
471   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
480   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
484   void legalizeOperands(MachineInstr &MI) const;
489   void moveToVALU(MachineInstr &MI) const;
491   void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
495                   MachineBasicBlock::iterator MI) const override;
499   unsigned getNumWaitStates(const MachineInstr &MI) const;
504   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
507   const MachineOperand *getNamedOperand(const MachineInstr &MI,  in getNamedOperand()  argument
509     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);  in getNamedOperand()
513   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {  in getNamedImmOperand()  argument
514     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);  in getNamedImmOperand()
515     return MI.getOperand(Idx).getImm();  in getNamedImmOperand()
521   bool isLowLatencyInstruction(const MachineInstr &MI) const;
522   bool isHighLatencyInstruction(const MachineInstr &MI) const;
530   unsigned getInstSizeInBytes(const MachineInstr &MI) const;