257   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
258   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
259   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
260   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
263   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
264   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
265   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1596 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {  in createGPRPairNode()  argument
1597   SDLoc dl(V0.getNode());  in createGPRPairNode()
1602   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createGPRPairNode()
1607 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createSRegPairNode()  argument
1608   SDLoc dl(V0.getNode());  in createSRegPairNode()
1613   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createSRegPairNode()
1618 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createDRegPairNode()  argument
1619   SDLoc dl(V0.getNode());  in createDRegPairNode()
1624   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createDRegPairNode()
1629 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createQRegPairNode()  argument
1630   SDLoc dl(V0.getNode());  in createQRegPairNode()
1635   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createQRegPairNode()
1640 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadSRegsNode()  argument
1642   SDLoc dl(V0.getNode());  in createQuadSRegsNode()
1649   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadSRegsNode()
1655 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadDRegsNode()  argument
1657   SDLoc dl(V0.getNode());  in createQuadDRegsNode()
1664   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadDRegsNode()
1670 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadQRegsNode()  argument
1672   SDLoc dl(V0.getNode());  in createQuadQRegsNode()
1679   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadQRegsNode()
2001       SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2004         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVST()
2012         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVST()
2055   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2061   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVST()
2167   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVLDSTLane()  local
2171       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVLDSTLane()
2173       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);  in SelectVLDSTLane()
2180       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2182       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2305   SDValue V0 = N->getOperand(FirstTblReg + 0);  in SelectVTBL()  local
2308     RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);  in SelectVTBL()
2316     RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVTBL()
3707     SDValue V0 = N->getOperand(0);  in Select()  local
3709     SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);  in Select()
4249     SDValue V0 = N->getOperand(i+1);  in tryInlineAsm()  local
4251     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();  in tryInlineAsm()