192         { RTLIB::OEQ_F32, "__eqsf2vfp",    ISD::SETNE },  in ARMTargetLowering()
193         { RTLIB::UNE_F32, "__nesf2vfp",    ISD::SETNE },  in ARMTargetLowering()
194         { RTLIB::OLT_F32, "__ltsf2vfp",    ISD::SETNE },  in ARMTargetLowering()
195         { RTLIB::OLE_F32, "__lesf2vfp",    ISD::SETNE },  in ARMTargetLowering()
196         { RTLIB::OGE_F32, "__gesf2vfp",    ISD::SETNE },  in ARMTargetLowering()
197         { RTLIB::OGT_F32, "__gtsf2vfp",    ISD::SETNE },  in ARMTargetLowering()
198         { RTLIB::UO_F32,  "__unordsf2vfp", ISD::SETNE },  in ARMTargetLowering()
202         { RTLIB::OEQ_F64, "__eqdf2vfp",    ISD::SETNE },  in ARMTargetLowering()
203         { RTLIB::UNE_F64, "__nedf2vfp",    ISD::SETNE },  in ARMTargetLowering()
204         { RTLIB::OLT_F64, "__ltdf2vfp",    ISD::SETNE },  in ARMTargetLowering()
205         { RTLIB::OLE_F64, "__ledf2vfp",    ISD::SETNE },  in ARMTargetLowering()
206         { RTLIB::OGE_F64, "__gedf2vfp",    ISD::SETNE },  in ARMTargetLowering()
207         { RTLIB::OGT_F64, "__gtdf2vfp",    ISD::SETNE },  in ARMTargetLowering()
208         { RTLIB::UO_F64,  "__unorddf2vfp", ISD::SETNE },  in ARMTargetLowering()
273       { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
275       { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
276       { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
277       { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
278       { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
279       { RTLIB::UO_F64,  "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
291       { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
293       { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
294       { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
295       { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
296       { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
297       { RTLIB::UO_F32,  "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
1332   case ISD::SETNE:  return ARMCC::NE;  in IntCCToARMCC()
1369   case ISD::SETNE:  in FPCCToARMCC()
3645                          SelectTrue, SelectFalse, ISD::SETNE);  in LowerSELECT()
3875       CC = ISD::SETNE;  in LowerSELECT_CC()
4029       CC = ISD::SETNE;  in OptimizeVFPBrcond()
4076       CC = ISD::SETNE;  in LowerBR_CC()
4092        CC == ISD::SETNE || CC == ISD::SETUNE)) {  in LowerBR_CC()
4894     case ISD::SETNE:  Invert = true; // Fallthrough  in LowerVSETCC()
4932     case ISD::SETNE:  Invert = true;  in LowerVSETCC()
10992     SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);  in PerformCMOVCombine()