464   if (Subtarget->hasNEON()) {  in ARMTargetLowering()
1013   if (Subtarget->hasNEON()) {  in ARMTargetLowering()
1264   if (Subtarget->hasNEON()) {  in getRegClassFor()
4251   bool UseNEON = !InGPR && Subtarget->hasNEON();  in LowerFCOPYSIGN()
4608     assert(ST->hasNEON());  in LowerCTTZ()
4786   assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");  in LowerCTPOP()
4806   assert(ST->hasNEON() && "unexpected vector shift");  in LowerShift()
5209   if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))  in LowerConstantFP()
7927         Subtarget->hasNEON()) {  in EmitStructByval()
8725   if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()  in AddCombineToVPADDL()
9279   if (BVN && Subtarget->hasNEON() &&  in PerformORCombine()
9311   if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&  in PerformORCombine()
10392   if (!Subtarget->hasNEON())  in PerformVCVTCombine()
10449   if (!Subtarget->hasNEON())  in PerformVDIVCombine()
10718   assert(ST->hasNEON() && "unexpected vector shift");  in PerformShiftCombine()
10755   if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {  in PerformExtendCombine()
11126     if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {  in allowsMisalignedMemoryAccesses()
11150   if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&  in getOptimalMemOpType()
11721   if (ConstraintVT.isVector() && Subtarget->hasNEON() &&  in LowerXConstraint()
12454   if (!Subtarget->hasNEON())  in canCombineStoreAndExtract()
12594   if (!Subtarget->hasNEON() || (VecSize != 64 && VecSize != 128) || EltIs64Bits)  in lowerInterleavedLoad()
12684   if (!Subtarget->hasNEON() || (SubVecSize != 64 && SubVecSize != 128) ||  in lowerInterleavedStore()