Lines Matching refs:Rm
1270 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1271 iir, opc, "\t$Rd, $Rn, $Rm",
1272 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1276 bits<4> Rm;
1282 let Inst{3-0} = Rm;
1343 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1344 iir, opc, "\t$Rd, $Rn, $Rm",
1349 bits<4> Rm;
1352 let Inst{3-0} = Rm;
1405 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1407 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1476 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1477 opc, "\t$Rn, $Rm",
1478 [(opnode GPR:$Rn, GPR:$Rm)]>,
1481 bits<4> Rm;
1488 let Inst{3-0} = Rm;
1537 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1538 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1539 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1542 bits<4> Rm;
1547 let Inst{3-0} = Rm;
1551 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1552 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1562 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1563 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1565 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1568 bits<4> Rm;
1575 let Inst{3-0} = Rm;
1579 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1580 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1606 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1607 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1608 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1613 bits<4> Rm;
1617 let Inst{3-0} = Rm;
1676 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1677 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1682 bits<4> Rm;
1685 let Inst{3-0} = Rm;
1920 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1921 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1924 bits<4> Rm;
1925 let Inst{3-0} = Rm;
2580 // {11-0} imm12/Rm
2598 // {11-0} imm12/Rm
2625 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2628 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2639 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2642 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2659 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2662 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2673 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2676 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2690 // {11-0} imm12/Rm
2709 // {11-0} imm12/Rm
2726 // {11-0} imm12/Rm
2745 // {11-0} imm12/Rm
2768 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2770 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2771 bits<5> Rm;
2772 let Inst{23} = Rm{4};
2776 let Inst{3-0} = Rm{3-0};
2851 // {11-0} imm12/Rm
2869 // {11-0} imm12/Rm
2948 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2951 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2966 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2969 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2981 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2984 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2997 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
3000 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3013 // {11-0} imm12/Rm
3032 // {11-0} imm12/Rm
3054 // {11-0} imm12/Rm
3073 // {11-0} imm12/Rm
3101 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3103 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3104 bits<5> Rm;
3105 let Inst{23} = Rm{4};
3108 let Inst{3-0} = Rm{3-0};
3250 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3251 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3253 bits<4> Rm;
3258 let Inst{3-0} = Rm;
3264 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3265 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3267 bits<4> Rm;
3271 let Inst{3-0} = Rm;
3371 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3372 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3541 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3542 string asm = "\t$Rd, $Rn, $Rm">
3547 bits<4> Rm;
3552 let Inst{3-0} = Rm;
3561 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3562 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3565 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3566 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3568 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3569 "\t$Rd, $Rm, $Rn">;
3571 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3572 "\t$Rd, $Rm, $Rn">;
3619 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3621 "\t$Rd, $Rn, $Rm", []>,
3625 bits<4> Rm;
3630 let Inst{11-8} = Rm;
3633 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3635 "\t$Rd, $Rn, $Rm, $Ra", []>,
3639 bits<4> Rm;
3645 let Inst{11-8} = Rm;
3766 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3767 "mvn", "\t$Rd, $Rm",
3768 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3770 bits<4> Rm;
3775 let Inst{3-0} = Rm;
3827 bits<4> Rm;
3830 let Inst{11-8} = Rm;
3838 bits<4> Rm;
3842 let Inst{11-8} = Rm;
3850 bits<4> Rm;
3854 let Inst{11-8} = Rm;
3863 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3864 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3865 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3872 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3875 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3876 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3881 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3882 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3883 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3891 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3893 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3894 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3897 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3898 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3899 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3902 bits<4> Rm;
3907 let Inst{11-8} = Rm;
3915 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3916 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3920 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3921 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3926 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3928 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3932 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3934 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3941 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3942 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3945 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3946 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3950 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3952 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3956 bits<4> Rm;
3960 let Inst{11-8} = Rm;
3967 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3969 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3973 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3975 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3983 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3984 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3985 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3990 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3991 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3997 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3998 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3999 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4003 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4004 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
4008 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4009 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4013 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4014 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
4018 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4019 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4021 (sext_inreg GPR:$Rm, i16)))]>,
4024 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4025 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4027 (sra GPR:$Rm, (i32 16))))]>,
4030 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4031 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4033 (sext_inreg GPR:$Rm, i16)))]>,
4036 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4037 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4039 (sra GPR:$Rm, (i32 16))))]>,
4042 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4043 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4047 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4048 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4057 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4058 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4061 (sext_inreg GPRnopc:$Rm, i16))))]>,
4065 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4066 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4069 (sra GPRnopc:$Rm, (i32 16)))))]>,
4073 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4074 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4077 (sext_inreg GPRnopc:$Rm, i16))))]>,
4081 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4082 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4085 (sra GPRnopc:$Rm, (i32 16)))))]>,
4089 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4090 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4095 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4096 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4107 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4108 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4112 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4113 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4117 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4118 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4122 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4123 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4131 bits<4> Rm;
4135 let Inst{11-8} = Rm;
4169 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4170 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4173 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4174 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4177 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4178 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4181 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4182 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4191 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4192 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4193 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4194 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4203 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4204 "sdiv", "\t$Rd, $Rn, $Rm",
4205 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4208 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4209 "udiv", "\t$Rd, $Rn, $Rm",
4210 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4217 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4218 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4219 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4222 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4223 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4224 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4228 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4229 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4230 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4234 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4235 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4236 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4246 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4247 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4248 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4252 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4253 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4254 (REVSH GPR:$Rm)>;
4257 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4258 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4260 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4266 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4267 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4268 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4269 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4274 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4275 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4277 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4305 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4306 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4307 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4311 bits<4> Rm;
4323 let Inst{3-0} = Rm;
4394 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4395 "cmn", "\t$Rn, $Rm",
4397 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4399 bits<4> Rm;
4406 let Inst{3-0} = Rm;
4489 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4491 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
5539 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5540 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5541 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5542 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5548 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5549 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5550 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5551 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5622 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5623 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
5625 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5626 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
5641 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5642 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5643 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5644 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5645 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5646 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5647 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5648 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5649 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5650 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5651 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5652 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5654 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5655 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5656 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5657 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5658 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5659 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5660 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5661 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5662 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5663 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5664 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5665 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5741 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5742 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5743 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5745 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5746 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5748 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5749 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5751 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5752 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5755 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5756 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5758 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5759 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5761 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5762 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5764 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5765 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5767 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5768 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5773 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5774 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5783 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5784 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
5786 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5787 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5790 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5791 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
5793 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5794 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
5796 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5797 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
5799 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5800 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,