Lines Matching refs:imm5

214 // t_addrmode_is4 := reg + imm5 * 4
226 // t_addrmode_is2 := reg + imm5 * 2
238 // t_addrmode_is1 := reg + imm5
658 // Loads: reg/reg and reg/imm5
668   def i : // reg/imm5
680 // Stores: reg/reg and reg/imm5
686   def i : // reg/imm5
962   T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
964                    "asr", "\t$Rd, $Rm, $imm5",
965                    [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
967   bits<5> imm5;
968   let Inst{10-6} = imm5;
1047   T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1049                    "lsl", "\t$Rd, $Rm, $imm5",
1050                    [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1052   bits<5> imm5;
1053   let Inst{10-6} = imm5;
1065   T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1067                    "lsr", "\t$Rd, $Rm, $imm5",
1068                    [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1070   bits<5> imm5;
1071   let Inst{10-6} = imm5;