Lines Matching refs:b01
599 let Inst{26-25} = 0b01;
612 let Inst{26-25} = 0b01;
683 let Inst{26-25} = 0b01;
696 let Inst{26-25} = 0b01;
803 let Inst{26-25} = 0b01;
817 let Inst{26-25} = 0b01;
846 let Inst{26-25} = 0b01;
859 let Inst{26-25} = 0b01;
942 let Inst{26-25} = 0b01;
957 let Inst{26-25} = 0b01;
1266 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1272 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1352 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1357 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1373 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1379 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1409 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1411 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1436 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1443 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1461 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1484 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1552 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1606 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1716 let Inst{24-23} = 0b01; // Increment After
1731 let Inst{24-23} = 0b01; // Increment After
1785 let Inst{24-23} = 0b01; // Increment After
1803 let Inst{24-23} = 0b01; // Increment After
1866 let Inst{26-25} = 0b01;
2298 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2311 let Inst{26-25} = 0b01;
2326 let Inst{26-25} = 0b01;
2330 let Inst{5-4} = 0b01; // Shift type.
2333 let Inst{7-6} = 0b01;
2341 let Inst{26-25} = 0b01;
2348 let Inst{7-6} = 0b01;
2485 let Inst{26-25} = 0b01;
2498 let Inst{26-25} = 0b01;
2694 let Inst{5-4} = 0b01;
2744 let Inst{5-4} = 0b01;
2774 let Inst{5-4} = 0b01;
2824 let Inst{5-4} = 0b01;
2955 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2960 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2964 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2969 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2987 let Inst{26-25} = 0b01;
3016 let Inst{26-25} = 0b01;
3064 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3065 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3103 let Inst{26-25} = 0b01;
3119 let Inst{26-25} = 0b01;
3774 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
4361 def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;