Lines Matching refs:Sd
105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
106 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
107 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
114 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
125 IIC_fpStore32, "vstr", "\t$Sd, $addr",
126 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),
133 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
341 let TwoOperandAliasConstraint = "$Sn = $Sd" in
343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
344 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
345 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
351 let TwoOperandAliasConstraint = "$Sn = $Sd" in
353 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
354 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
363 let TwoOperandAliasConstraint = "$Sn = $Sd" in
365 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
366 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
367 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
373 let TwoOperandAliasConstraint = "$Sn = $Sd" in
375 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
376 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
385 let TwoOperandAliasConstraint = "$Sn = $Sd" in
387 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
388 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
389 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
391 let TwoOperandAliasConstraint = "$Sn = $Sd" in
393 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
394 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
403 let TwoOperandAliasConstraint = "$Sn = $Sd" in
405 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
406 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
407 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
413 let TwoOperandAliasConstraint = "$Sn = $Sd" in
415 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
416 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
425 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
426 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
427 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
435 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
442 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
443 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
448 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
449 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
450 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
470 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
471 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
476 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
477 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
478 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
507 (outs), (ins SPR:$Sd, SPR:$Sm),
508 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
509 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
516 (outs), (ins SPR:$Sd, SPR:$Sm),
517 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
528 (outs), (ins SPR:$Sd, SPR:$Sm),
529 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
537 (outs), (ins SPR:$Sd, SPR:$Sm),
538 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
552 (outs SPR:$Sd), (ins SPR:$Sm),
553 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
554 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
561 (outs SPR:$Sd), (ins SPR:$Sm),
562 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
575 (outs), (ins SPR:$Sd),
576 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
577 [(arm_cmpfp0 SPR:$Sd)]> {
587 (outs), (ins SPR:$Sd),
588 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
604 (outs), (ins SPR:$Sd),
605 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
616 (outs), (ins SPR:$Sd),
617 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
642 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
643 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
644 [(set SPR:$Sd, (fround DPR:$Dm))]> {
646 bits<5> Sd;
652 let Inst{15-12} = Sd{4-1};
653 let Inst{22} = Sd{0};
667 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
668 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
672 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
673 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
677 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
678 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
682 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
683 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
700 (outs SPR:$Sd), (ins DPR:$Dm),
701 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
704 bits<5> Sd;
710 let Inst{15-12} = Sd{4-1};
711 let Inst{22} = Sd{0};
727 (outs SPR:$Sd), (ins DPR:$Dm),
728 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
731 bits<5> Sd;
735 let Inst{15-12} = Sd{4-1};
736 let Inst{22} = Sd{0};
757 (outs SPR:$Sd), (ins SPR:$Sm),
758 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
765 (outs SPR:$Sd), (ins SPR:$Sm),
766 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
773 (outs SPR:$Sd), (ins SPR:$Sm),
774 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
781 (outs SPR:$Sd), (ins SPR:$Sm),
782 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
789 (outs SPR:$Sd), (ins DPR:$Dm),
790 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
804 (outs SPR:$Sd), (ins DPR:$Dm),
805 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
852 (outs SPR:$Sd), (ins SPR:$Sm),
853 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
854 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
861 (outs SPR:$Sd), (ins SPR:$Sm),
862 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
867 (outs SPR:$Sd), (ins SPR:$Sm),
868 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
876 (outs SPR:$Sd), (ins SPR:$Sm),
877 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
878 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
892 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
893 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
895 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
896 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
911 (outs SPR:$Sd), (ins SPR:$Sm),
912 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
918 (outs SPR:$Sd), (ins SPR:$Sm),
919 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
920 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
933 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
934 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
952 (outs SPR:$Sd), (ins SPR:$Sm),
953 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
954 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
957 (outs SPR:$Sd), (ins SPR:$Sm),
958 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
967 (outs SPR:$Sd), (ins SPR:$Sm),
968 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
972 (outs SPR:$Sd), (ins SPR:$Sm),
973 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
977 (outs SPR:$Sd), (ins SPR:$Sm),
978 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
1225 bits<5> Sd;
1231 let Inst{15-12} = Sd{4-1};
1232 let Inst{22} = Sd{0};
1242 bits<5> Sd;
1248 let Inst{15-12} = Sd{4-1};
1249 let Inst{22} = Sd{0};
1270 (outs SPR:$Sd),(ins SPR:$Sm),
1271 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1287 (outs SPR:$Sd), (ins SPR:$Sm),
1288 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1309 (outs SPR:$Sd), (ins SPR:$Sm),
1310 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1326 (outs SPR:$Sd), (ins SPR:$Sm),
1327 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1341 bits<5> Sd;
1347 let Inst{15-12} = Sd{4-1};
1348 let Inst{22} = Sd{0};
1360 bits<5> Sd;
1366 let Inst{15-12} = Sd{4-1};
1367 let Inst{22} = Sd{0};
1377 bits<5> Sd;
1383 let Inst{15-12} = Sd{4-1};
1384 let Inst{22} = Sd{0};
1391 (outs SPR:$Sd), (ins DPR:$Dm),
1392 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1406 (outs SPR:$Sd), (ins SPR:$Sm),
1407 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1424 (outs SPR:$Sd), (ins SPR:$Sm),
1425 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1431 (outs SPR:$Sd), (ins DPR:$Dm),
1432 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1446 (outs SPR:$Sd), (ins SPR:$Sm),
1447 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1464 (outs SPR:$Sd), (ins SPR:$Sm),
1465 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1474 (outs SPR:$Sd), (ins DPR:$Dm),
1475 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1476 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1481 (outs SPR:$Sd), (ins SPR:$Sm),
1482 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1483 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1488 (outs SPR:$Sd), (ins SPR:$Sm),
1489 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1495 (outs SPR:$Sd), (ins DPR:$Dm),
1496 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1497 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1502 (outs SPR:$Sd), (ins SPR:$Sm),
1503 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1504 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1509 (outs SPR:$Sd), (ins SPR:$Sm),
1510 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1706 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1707 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1708 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1710 RegConstraint<"$Sdin = $Sd">,
1718 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1719 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
1721 RegConstraint<"$Sdin = $Sd">,
1740 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1741 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1742 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1744 RegConstraint<"$Sdin = $Sd">,
1752 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1753 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
1755 RegConstraint<"$Sdin = $Sd">,
1774 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1775 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1776 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1778 RegConstraint<"$Sdin = $Sd">,
1786 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1787 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
1789 RegConstraint<"$Sdin = $Sd">,
1808 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1809 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1810 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1811 RegConstraint<"$Sdin = $Sd">,
1819 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1820 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
1822 RegConstraint<"$Sdin = $Sd">,
1844 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1845 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1846 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1848 RegConstraint<"$Sdin = $Sd">,
1855 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1856 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
1858 RegConstraint<"$Sdin = $Sd">,
1886 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1887 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1888 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1890 RegConstraint<"$Sdin = $Sd">,
1897 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1898 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
1900 RegConstraint<"$Sdin = $Sd">,
1935 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1936 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1937 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1939 RegConstraint<"$Sdin = $Sd">,
1946 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1947 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
1949 RegConstraint<"$Sdin = $Sd">,
1984 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1985 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1986 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1987 RegConstraint<"$Sdin = $Sd">,
1994 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1995 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
1997 RegConstraint<"$Sdin = $Sd">,
2042 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2044 [(set (f32 SPR:$Sd),
2046 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
2163 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2165 "vmov", ".f32\t$Sd, $imm",
2166 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2167 bits<5> Sd;
2171 let Inst{22} = Sd{0};
2174 let Inst{15-12} = Sd{4-1};
2181 def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
2183 "vmov", ".f16\t$Sd, $imm",
2185 bits<5> Sd;
2189 let Inst{22} = Sd{0};
2192 let Inst{15-12} = Sd{4-1};
2252 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
2253 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2256 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
2257 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2262 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2266 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
2267 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2268 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
2269 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2296 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
2297 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2307 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
2308 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;