Lines Matching refs:EvenReg

1581   unsigned EvenReg = MI->getOperand(0).getReg();
1583   unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
1588   bool Errata602117 = EvenReg == BaseReg &&
1623         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1630         .addReg(EvenReg,
1651         (TRI->regsOverlap(EvenReg, BaseReg))) {
1658                     EvenReg, EvenDeadKill, false,
1662       if (OddReg == EvenReg && EvenDeadKill) {
1670       if (EvenReg == BaseReg)
1673                     EvenReg, EvenDeadKill, EvenUndef,
1973                           unsigned &NewOpc, unsigned &EvenReg,