312     bool isReg() const { return Kind == CV_Register; }  in isReg()  function in __anonfb58bf460111::CountValue
316       assert(isReg() && "Wrong CountValue accessor");  in getReg()
320       assert(isReg() && "Wrong CountValue accessor");  in getSubReg()
329       if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }  in print()
644   if (Op1.isReg()) {  in getLoopTripCount()
664   if (InitialValue->isReg()) {  in getLoopTripCount()
671   if (EndValue->isReg()) {  in getLoopTripCount()
698   if (Start->isReg()) {  in computeCount()
704   if (End->isReg()) {  in computeCount()
711   if (!Start->isReg() && !Start->isImm())  in computeCount()
713   if (!End->isReg() && !End->isImm())  in computeCount()
811   bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)  in computeCount()
812   bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)  in computeCount()
849   if (Start->isReg()) {  in computeCount()
960     if (!MO.isReg() || !MO.isDef())  in isInvalidLoopOperation()
1001     if (!MO.isReg() || !MO.isDef())  in isDead()
1021       if (!OPO.isReg() || !OPO.isDef())  in isDead()
1056       if (!MO.isReg() || !MO.isDef())  in removeIfDead()
1172   if (TripCount->isReg()) {  in convertToHardwareLoop()
1208   if (TripCount->isReg()) {  in convertToHardwareLoop()
1305       if (MO.isReg() && MO.isUse()) {  in orderBumpCompare()
1382   if (!InitVal->isReg())  in loopCountMayWrapOrUnderFlow()
1465   if (!MO.isReg())  in checkForImmediate()
1547   assert(MO.isReg());  in setImmediate()
1666   if (!Cond[CSz-1].isReg())  in fixupInductionVariable()
1684     if (MO.isReg()) {  in fixupInductionVariable()
1733           if (MO.isReg() && MO.getReg() == RB.first) {  in fixupInductionVariable()
1741           } else if (MO.isReg()) {  in fixupInductionVariable()
1799         if (MO.isReg() && MO.getReg() == RB.first) {  in fixupInductionVariable()