Lines Matching refs:v8i64
197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
413 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || in RetCC_Hexagon()
543 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
901 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 || in getIndexedAddressParts()
1118 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1758 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2876 case MVT::v8i64: in getRegForInlineAsmConstraint()
2886 case MVT::v8i64: in getRegForInlineAsmConstraint()
3037 case MVT::v8i64: in allowsMisalignedMemoryAccesses()
3058 case MVT::v8i64: in findRepresentativeClass()