Lines Matching refs:opc
1 class Enc_COPROC_VX_3op_v<bits<15> opc> : OpcodeHexagon {
6 let Inst{31-16} = { opc{14-4}, src2};
7 let Inst{13-0} = { opc{3}, src1, opc{2-0}, dst};
196 class Enc_COPROC_VX_cmp<bits<13> opc> : OpcodeHexagon {
201 let Inst{31-16} = { 0b00011, opc{12-7}, src2{4-0} };
202 let Inst{13-0} = { opc{6}, src1{4-0}, opc{5-0}, dst{1-0} };
244 class Enc_COPROC_VX_p2op<bits<5> opc> : OpcodeHexagon {
249 let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} };
250 let Inst{13-0} = { 1, src2{4-0}, opc{2-0}, dst{4-0} };
266 class Enc_COPROC_VX_2op<bits<6> opc> : OpcodeHexagon {
270 let Inst{31-16} = { 0b00011110000000, opc{5-4} };
271 let Inst{13-0} = { opc{3}, src1{4-0}, opc{2-0}, dst{4-0} };
300 class Enc_COPROC_VMEM_vL32_b_ai<bits<4> opc> : OpcodeHexagon {
307 let Inst{31-16} = { 0b001010000, opc{3}, 0, src1{4-0} };
308 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} };
319 class Enc_COPROC_VMEM_vL32_b_ai_128B<bits<4> opc> : OpcodeHexagon {
326 let Inst{31-16} = { 0b001010000, opc{3}, 0, src1{4-0} };
327 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} };
338 class Enc_COPROC_VMEM_vS32_b_ai_64B<bits<4> opc> : OpcodeHexagon {
345 let Inst{31-16} = { 0b001010000, opc{3}, 1, src1{4-0} };
346 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} };
349 class Enc_COPROC_VMEM_vS32_b_ai_128B<bits<4> opc> : OpcodeHexagon {
356 let Inst{31-16} = { 0b001010000, opc{3}, 1, src1{4-0} };
357 let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} };
368 class Enc_COPROC_VMEM_vS32b_n_ew_ai_64B<bits<1> opc> : OpcodeHexagon {
375 let Inst{31-16} = { 0b001010000, opc{0}, 1, src1{4-0} };
382 class Enc_COPROC_VMEM_vS32b_n_ew_ai_128B<bits<1> opc> : OpcodeHexagon {
389 let Inst{31-16} = { 0b001010000, opc{0}, 1, src1{4-0} };
396 class Enc_COPROC_VMEM_vS32_b_pred_ai<bits<5> opc> : OpcodeHexagon {
404 let Inst{31-16} = { 0b001010001, opc{4-3}, src2{4-0} };
405 let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} };
408 class Enc_COPROC_VMEM_vS32_b_pred_ai_128B<bits<5> opc> : OpcodeHexagon {
416 let Inst{31-16} = { 0b001010001, opc{4-3}, src2{4-0} };
417 let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} };
442 class Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<bits<4> opc> : OpcodeHexagon {
450 let Inst{31-16} = { 0b001010001, opc{3}, 1, src2{4-0} };
451 let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
459 class Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<bits<4> opc> : OpcodeHexagon {
467 let Inst{31-16} = { 0b001010001, opc{3}, 1, src2{4-0} };
468 let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
478 class Enc_COPROC_VMEM_vL32_b_pi<bits<4> opc> : OpcodeHexagon {
485 let Inst{31-16} = { 0b001010010, opc{3}, 0, src1{4-0} };
486 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
497 class Enc_COPROC_VMEM_vL32_b_pi_128B<bits<4> opc> : OpcodeHexagon {
504 let Inst{31-16} = { 0b001010010, opc{3}, 0, src1{4-0} };
505 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
519 class Enc_COPROC_VMEM_vS32_b_pi<bits<4> opc> : OpcodeHexagon {
526 let Inst{31-16} = { 0b001010010, opc{3}, 1, src1{4-0} };
527 let Inst{10-0} = {src2_vector{2-0}, opc{2-0}, src3{4-0} };
534 class Enc_COPROC_VMEM_vS32_b_pi_128B<bits<4> opc> : OpcodeHexagon {
541 let Inst{31-16} = { 0b001010010, opc{3}, 1, src1{4-0} };
542 let Inst{10-0} = {src2_vector{2-0}, opc{2-0}, src3{4-0} };
551 class Enc_COPROC_VMEM_vS32b_n_ew_pi<bits<1> opc> : OpcodeHexagon {
558 let Inst{31-16} = { 0b001010010, opc{0}, 1, src1{4-0} };
565 class Enc_COPROC_VMEM_vS32b_n_ew_pi_128B<bits<1> opc> : OpcodeHexagon {
572 let Inst{31-16} = { 0b001010010, opc{0}, 1, src1{4-0} };
581 class Enc_COPROC_VMEM_vS32_b_pred_pi<bits<5> opc> : OpcodeHexagon {
589 let Inst{31-16} = { 0b001010011, opc{4-3}, src2{4-0} };
590 let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} };
606 class Enc_COPROC_VMEM_vS32_b_pred_pi_128B<bits<5> opc> : OpcodeHexagon {
614 let Inst{31-16} = { 0b001010011, opc{4-3}, src2{4-0} };
615 let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} };
629 class Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<bits<4> opc> : OpcodeHexagon {
637 let Inst{31-16} = { 0b001010011, opc{3}, 1, src2{4-0} };
638 let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
646 class Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<bits<4> opc> : OpcodeHexagon {
654 let Inst{31-16} = { 0b001010011, opc{3}, 1, src2{4-0} };
655 let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
663 class Enc_LD_load_m<bits<13> opc> : OpcodeHexagon {
668 let Inst{31-16} = { opc{12}, 0, opc{11-10}, 1, opc{9-4}, src1{4-0} };
669 let Inst{13-0} = { src2{0}, 0b000, opc{3}, 0, opc{2-0}, dst{4-0} };
680 class Enc_COPROC_VMEM_vS32_b_ppu<bits<4> opc> : OpcodeHexagon {
685 let Inst{31-16} = { 0b001010110, opc{3}, 1, src1{4-0} };
686 let Inst{13-0} = { src2{0}, 0b00000, opc{2-0}, src3{4-0} };
693 class Enc_COPROC_VMEM_vS32b_new_ppu<bits<1> opc> : OpcodeHexagon {
698 let Inst{31-16} = { 0b001010110, opc{0}, 1, src1{4-0} };
705 class Enc_COPROC_VMEM_vS32_b_pred_ppu<bits<5> opc> : OpcodeHexagon {
711 let Inst{31-16} = { 0b001010111, opc{4-3}, src2{4-0} };
712 let Inst{13-0} = { src3{0}, src1{1-0}, 0b000, opc{2-0}, src4{4-0} };
726 class Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<bits<4> opc> : OpcodeHexagon {
732 let Inst{31-16} = { 0b001010111, opc{3}, 1, src2{4-0} };
733 let Inst{13-0} = { src3{0}, src1{1-0}, 0b00001, opc{2-0}, src4{2-0} };
742 class Enc_COPROC_VX_4op_i<bits<5> opc> : OpcodeHexagon {
748 let Inst{31-16} = { 0b00011001, opc{4-2}, src2{4-0} };
749 let Inst{13-0} = { opc{1}, src1{4-0}, 1, opc{0}, src3{0}, dst{4-0} };
759 class Enc_COPROC_VX_vandqrt<bits<5> opc> : OpcodeHexagon {
764 let Inst{31-16} = { 0b00011001, opc{4-3}, 1, src2{4-0} };
765 let Inst{13-0} = { opc{2}, 0b000, src1{1-0}, opc{1-0}, 1, dst{4-0} };
771 class Enc_COPROC_VX_cards<bits<2> opc> : OpcodeHexagon {
777 let Inst{13-0} = { 1, src1{4-0}, 0, opc{1-0}, src2{4-0} };
784 class Enc_COPROC_VX_v_cmov<bits<1> opc> : OpcodeHexagon {
789 let Inst{31-16} = { 0b0001101000, opc{0}, 0b00000 };
796 class Enc_X_p3op<bits<8> opc> : OpcodeHexagon {
802 let Inst{31-16} = { opc{7-5}, 0b1101, opc{4}, 0, opc{3-2}, src3{4-0} };
803 let Inst{13-0} = { opc{1}, src2{4-0}, opc{0}, src1{1-0}, dst{4-0} };
809 class Enc_COPROC_VX_4op_r<bits<4> opc> : OpcodeHexagon {
816 let Inst{13-0} = { opc{3}, src1{4-0}, opc{2-0}, dst{4-0} };
835 class Enc_S_3op_valign_i<bits<9> opc> : OpcodeHexagon {
841 let Inst{31-16} = { opc{8-7}, 0, opc{6-3}, 0b00, opc{2-1}, src2{4-0} };
842 let Inst{13-0} = { opc{0}, src1{4-0}, src3{2-0}, dst{4-0} };
854 class Enc_COPROC_VX_3op_q<bits<3> opc> : OpcodeHexagon {
860 let Inst{13-0} = { 0b0000, src1{1-0}, 0b000, opc{2-0}, dst{1-0} };
877 class Enc_COPROC_VX_4op_q<bits<1> opc> : OpcodeHexagon {
883 let Inst{31-16} = { 0b000111101, opc{0}, 1, src3{4-0} };
890 class Enc_X_2op<bits<16> opc> : OpcodeHexagon {
894 let Inst{31-16} = { opc{15-5}, src1{4-0} };
895 let Inst{13-0} = { opc{4-3}, 0b0000, opc{2-0}, dst{4-0} };
903 class Enc_CR_2op_r<bits<12> opc> : OpcodeHexagon {
907 let Inst{31-16} = { opc{11}, 0, opc{10-7}, 0, opc{6-3}, src1{4-0} };
908 let Inst{13-0} = { opc{2}, 0b000000, opc{1}, 0b000, opc{0}, dst{1-0} };
914 class Enc_S_3op_i6<bits<9> opc> : OpcodeHexagon {
919 let Inst{31-16} = { 0b1000, opc{8-6}, 0, opc{5-3}, src1{4-0} };
920 let Inst{13-0} = { src2{5-0}, opc{2-0}, dst{4-0} };
930 class Enc_X_3op_r<bits<15> opc> : OpcodeHexagon {
935 let Inst{31-16} = { opc{14-4}, src1{4-0} };
936 let Inst{13-0} = { opc{3}, src2{4-0}, opc{2-0}, dst{4-0} };
948 class Enc_no_operands<bits<25> opc> : OpcodeHexagon {
950 let Inst{31-16} = { opc{24-10}, 0 };
951 let Inst{13-0} = { opc{9-7}, 0b000, opc{6-0}, 0 };
959 class Enc_J_jumpr<bits<13> opc> : OpcodeHexagon {
962 let Inst{31-16} = { opc{12-6}, 0, opc{5-3}, src1{4-0} };
963 let Inst{13-0} = { 0b00, opc{2}, 0b0000, opc{1-0}, 0b00000 };
969 class Enc_ST_l2gclean_pa<bits<2> opc> : OpcodeHexagon {
972 let Inst{31-16} = { 0b101001101, opc{1-0}, 0b00000 };
989 class Enc_X_4op_r<bits<8> opc> : OpcodeHexagon {
995 let Inst{31-16} = { 0b11, opc{7}, 0, opc{6-5}, 1, opc{4-1}, src1{4-0} };
996 let Inst{13-0} = { 0, src2{4-0}, opc{0}, src3{1-0}, dst{4-0} };