Lines Matching refs:Rss

857                 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
858 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
863 bits<5> Rss;
870 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
871 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
877 // Rdd=vadd[u][bhw](Rss,Rtt)
884 // Rdd=vadd[u][bhw](Rss,Rtt):sat
893 // Rdd=vavg[u][bhw](Rss,Rtt)
902 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
912 // Rdd=vnavg[bh](Rss,Rtt)
918 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
926 // Rdd=vsub[u][bh](Rss,Rtt)
933 // Rdd=vsub[u][bh](Rss,Rtt):sat
941 // Rdd=vmax[u][bhw](Rss,Rtt)
949 // Rdd=vmin[u][bhw](Rss,Rtt)
963 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
964 "$Pd = "#Str#"($Rss, $Rtt)", [],
967 bits<5> Rss;
976 let Inst{20-16} = Rss;
981 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
982 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
2560 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2561 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2566 bits<5> Rss;
2575 let Inst{20-16} = Rss;
2579 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2584 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2588 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2592 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2596 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2602 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2608 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2614 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2846 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2847 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2850 bits<5> Rss;
2859 let Inst{20-16} = Rss;
2865 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2866 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2869 bits<5> Rss;
2878 let Inst{20-16} = Rss;
2883 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2884 "$Rdd = "#opc#"($Rtt, $Rss)",
2887 bits<5> Rss;
2896 let Inst{20-16} = Rss;
2904 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2908 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2911 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
2915 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2927 // Rdd[+]=vrmpyh(Rss,Rtt)
2939 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2940 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2944 bits<5> Rss;
2953 let Inst{20-16} = Rss;
2960 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2961 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2965 bits<5> Rss;
2974 let Inst{20-16} = Rss;
2979 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
2991 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
3003 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
3009 // Rxx+=vdmpy(Rss,Rtt)[:sat]
3014 // Rxx+=vcmpy[ir](Rss,Rtt):sat
4069 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
4070 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
4071 bits<5> Rss;
4076 let Inst{20-16} = Rss;
4151 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
4158 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
4897 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4901 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)).
4905 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)).
4963 // Rss <= Rtt -> !(Rss > Rtt).
4978 // Map cmpne(Rss) -> !cmpew(Rss).
4993 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
5023 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
5046 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
5169 // Rxx[+-&|]=asr(Rss,#u6)
5170 // Rxx[+-&|^]=lsr(Rss,#u6)
5171 // Rxx[+-&|^]=asl(Rss,#u6)
5176 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5177 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5180 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5183 bits<5> Rss;
5193 let Inst{20-16} = Rss;
5198 // Rxx[+-&|]=asr(Rss,Rt)
5199 // Rxx[+-&|^]=lsr(Rss,Rt)
5200 // Rxx[+-&|^]=asl(Rss,Rt)
5201 // Rxx[+-&|^]=lsl(Rss,Rt)
5206 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5207 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5210 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5213 bits<5> Rss;
5220 let Inst{20-16} = Rss;
5333 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5334 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5337 bits<5> Rss;
5345 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5346 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5402 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5428 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5429 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5435 bits<5> Rss;
5441 let Inst{20-16} = Rss;
5455 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5456 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5459 bits<5> Rss;
5467 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5468 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5534 // Rxx=insert(Rss,Rtt)
5535 // Rxx=insert(Rss,#u6,#U6)
5623 // Rdd=extractu(Rss,Rtt)
5624 // Rdd=extractu(Rss,#u6,#U6)