Lines Matching refs:b00
88 let Inst{3-2} = 0b00;
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
272 let Inst{3-2} = 0b00;
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
455 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
499 let Inst{27-26} = 0b00;
1069 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1073 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1078 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1082 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1087 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1093 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1100 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1106 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1357 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1404 let Inst{22-21} = 0b00;
1572 let Inst{9-8} = !if (isPred, Pu, 0b00);
1853 let Inst{13-12} = 0b00;
1973 let Inst{13-12} = 0b00;
2202 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2338 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2339 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2348 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2349 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2358 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2359 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2370 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2371 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2379 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2380 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2423 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2424 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2433 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2434 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2443 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2444 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2453 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2454 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2463 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2464 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2473 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2474 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2517 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2522 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2527 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2532 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2537 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2542 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2547 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2552 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2756 let Inst{27-26} = 0b00;
3048 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
3053 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
3058 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
3063 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
3069 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
3074 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
3731 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3798 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3872 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3919 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3920 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3921 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3922 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3940 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3941 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3942 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3943 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
4093 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
4094 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
4095 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
4096 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
4124 let Inst{25-24} = 0b00;
4202 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
4653 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
5252 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5266 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5285 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5319 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5320 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5321 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5388 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5404 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5411 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5421 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5450 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5492 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5625 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5631 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5684 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;