Lines Matching refs:ImmOp
1260 Operand ImmOp, bits<2>MajOp>
1262 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1342 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1345 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1411 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1413 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1422 string ImmOpStr = !cast<string>(ImmOp);
1444 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1448 ImmOp:$offset, IntRegs:$src3),
1459 string ImmOpStr = !cast<string>(ImmOp);
1479 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1481 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1484 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1487 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1490 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1493 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1494 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
2862 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2865 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2893 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2896 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2923 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2924 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2925 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2926 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2927 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2931 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2932 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2933 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2934 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2935 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2938 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2939 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2940 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
3335 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3337 : STInst<(outs), (ins ImmOp:$addr, RC:$src),
3344 string ImmOpStr = !cast<string>(ImmOp);
3402 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3406 string ImmOpStr = !cast<string>(ImmOp);
3423 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3426 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3444 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp>
3445 : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src),
3452 string ImmOpStr = !cast<string>(ImmOp);
3505 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3508 string ImmOpStr = !cast<string>(ImmOp);
3524 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3528 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3570 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3571 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
3579 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3585 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3588 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp> ;
3647 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3649 : LDInst <(outs RC:$dst), (ins ImmOp:$addr),
3656 string ImmOpStr = !cast<string>(ImmOp);
3673 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3677 string ImmOpStr = !cast<string>(ImmOp);
3734 Operand ImmOp, bits<3> MajOp> {
3737 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3769 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3771 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {