Lines Matching refs:b01
238 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
241 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
409 let Inst{13-12} = 0b01;
751 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
848 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
906 let Inst{27-26} = 0b01;
965 let Inst{27-26} = 0b01;
1025 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1158 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1364 u6_1Ext, 0b01>, AddrModeRel;
1502 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1532 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1808 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1812 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1969 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1975 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1976 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1977 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1978 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
2385 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2599 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2603 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2604 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2605 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2609 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2659 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2677 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2876 !if (!eq(opcBits, 0b01), offset{6-1},
2908 !if (!eq(opcBits, 0b01), offset{6-1},
2925 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2933 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2949 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
3165 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3548 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3549 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3559 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3596 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3607 u16_1Imm, 0b01, 1>, PredNewRel;
4159 !if (!eq(op, "gt"), 0b01,
4218 !if (!eq(op, "gt"), 0b01, 0));