Lines Matching refs:ImmOp
121 class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp,
123 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
161 class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
162 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
190 class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp,
193 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
252 class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC,
255 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
291 class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC,
294 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
338 class T_vload_pi<string asmStr, Operand ImmOp, RegisterClass RC>
340 (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
403 class T_vstore_pi <string mnemonic, string baseOp, Operand ImmOp,
406 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
447 class T_vstore_new_pi <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
449 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
480 class T_vstore_pred_pi <string mnemonic, string baseOp, Operand ImmOp,
483 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
543 class T_vstore_qpred_pi <Operand ImmOp, RegisterClass RC, bit isPredNot = 0,
546 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
584 class T_vstore_new_pred_pi <string baseOp, Operand ImmOp, RegisterClass RC,
587 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
778 class STrivv_template<string mnemonic, Operand ImmOp, RegisterClass RC>:
779 VSTInst<(outs), (ins IntRegs:$addr, ImmOp:$off, RC:$src),
854 class LDrivv_template<string mnemonic, Operand ImmOp, RegisterClass RC>
855 : V6_LDInst <(outs RC:$dst), (ins IntRegs:$addr, ImmOp:$off),
2094 class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp >
2095 : SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>;
2107 class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp>
2108 : SInst2 <(outs RC:$dst), (ins RC:$_src_, RC:$src1, ImmOp:$src2),