Lines Matching refs:IntRegs
60 : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2),
65 : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2),
123 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
162 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
193 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
255 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
294 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
339 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
340 (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
405 : V6_STInst <(outs IntRegs:$_dst_),
406 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
448 : V6_STInst <(outs IntRegs:$_dst_),
449 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
482 : V6_STInst<(outs IntRegs:$_dst_),
483 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
545 : V6_STInst <(outs IntRegs:$_dst_),
546 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
586 : V6_STInst <(outs IntRegs:$_dst_),
587 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
632 : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
633 (ins IntRegs:$src1, ModRegs:$src2), asmStr, [],
666 : V6_STInst <(outs IntRegs:$_dst_),
667 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
688 : V6_STInst <(outs IntRegs:$_dst_),
689 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
704 : V6_STInst<(outs IntRegs:$_dst_),
705 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
736 : V6_STInst <(outs IntRegs:$_dst_),
737 (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
755 : V6_STInst <(outs IntRegs:$_dst_),
756 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
779 VSTInst<(outs), (ins IntRegs:$addr, ImmOp:$off, RC:$src),
788 def : Pat<(store (VTSgl VecDblRegs:$src1), IntRegs:$addr),
789 (STrivv_indexed IntRegs:$addr, #0, (VTSgl VecDblRegs:$src1))>,
792 def : Pat<(store (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
793 (STrivv_indexed_128B IntRegs:$addr, #0,
806 def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
807 (V6_vS32b_ai IntRegs:$addr, #0, (VTSgl VectorRegs:$src1))>,
809 def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
810 (V6_vS32Ub_ai IntRegs:$addr, #0, (VTSgl VectorRegs:$src1))>,
814 def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
815 (V6_vS32b_ai_128B IntRegs:$addr, #0, (VTDbl VectorRegs128B:$src1))>,
817 def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
818 (V6_vS32Ub_ai_128B IntRegs:$addr, #0, (VTDbl VectorRegs128B:$src1))>,
824 (add IntRegs:$src2, s4_6ImmPred:$offset)),
825 (V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset,
829 (add IntRegs:$src2, s4_6ImmPred:$offset)),
830 (V6_vS32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset,
836 (add IntRegs:$src2, s4_7ImmPred:$offset)),
837 (V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
841 (add IntRegs:$src2, s4_7ImmPred:$offset)),
842 (V6_vS32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
855 : V6_LDInst <(outs RC:$dst), (ins IntRegs:$addr, ImmOp:$off),
864 def : Pat < (VTSgl (load IntRegs:$addr)),
865 (LDrivv_indexed IntRegs:$addr, #0) >,
868 def : Pat < (VTDbl (load IntRegs:$addr)),
869 (LDrivv_indexed_128B IntRegs:$addr, #0) >,
880 def : Pat < (VTSgl (alignedload IntRegs:$addr)),
881 (V6_vL32b_ai IntRegs:$addr, #0) >,
883 def : Pat < (VTSgl (unalignedload IntRegs:$addr)),
884 (V6_vL32Ub_ai IntRegs:$addr, #0) >,
888 def : Pat < (VTDbl (alignedload IntRegs:$addr)),
889 (V6_vL32b_ai_128B IntRegs:$addr, #0) >,
891 def : Pat < (VTDbl (unalignedload IntRegs:$addr)),
892 (V6_vL32Ub_ai_128B IntRegs:$addr, #0) >,
897 def : Pat<(VTDbl (alignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
898 (V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
900 def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
901 (V6_vL32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
904 def : Pat<(VTSgl (alignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
905 (V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
907 def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
908 (V6_vL32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
922 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs:$src1),
928 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
934 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs128B:$src1),
940 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
950 (ins IntRegs:$base, s32Imm:$offset),
955 (ins IntRegs:$base, s32Imm:$offset),
960 (ins IntRegs:$base, s32Imm:$offset),
965 (ins IntRegs:$base, s32Imm:$offset),
975 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
980 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
989 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs:$src1),
994 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs128B:$src1),
1004 (ins IntRegs:$base, s32Imm:$offset),
1009 (ins IntRegs:$base, s32Imm:$offset),
1018 (ins IntRegs:$base, s32Imm:$offset),
1023 (ins IntRegs:$base, s32Imm:$offset),
1047 def : Pat <(v16i32 (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs),
1050 (v16i32 (VSelectPseudo_V6 (i32 (C2_cmpeq (i32 IntRegs:$lhs),
1051 (i32 IntRegs:$rhs))),
1058 : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
1319 !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>;
1323 T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>;
1326 T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1329 T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>;
1332 T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1785 (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1Imm:$src3),
1809 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1Imm:$src3),
1832 (ins RC:$src1, RC:$src2, IntRegs:$src3),
2028 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
2038 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
2048 (ins RCin:$src1, IntRegs:$src2),
2057 : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1),
2067 : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1),
2078 : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1),
2086 : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
2098 : T_HVX_rol <asmString, IntRegs, u5Imm>;
2115 : T_HVX_rol_acc <asmString, IntRegs, u5Imm>;
2143 : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2),
2163 class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>;
2176 def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1),