Lines Matching refs:def
17 def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18 def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
21 def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22 def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
25 def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26 def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
29 def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30 def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
34 def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35 def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
38 def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>;
39 def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>;
43 def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>;
45 def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>;
49 def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
51 def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
54 def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
56 def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
58 def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
60 def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
63 def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>;
64 def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>;
65 def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>;
66 def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>;
67 def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>;
69 def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>;
70 def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>;
73 def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>;
75 def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>;
76 def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>;
77 def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>;
79 def: T_Q_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
80 def: T_Q_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
81 def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
83 def : T_Q_PI_pat<A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi>;
84 def : T_Q_PI_pat<A4_vcmpbgti, int_hexagon_A4_vcmpbgti>;
85 def : T_Q_PI_pat<A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui>;
86 def : T_Q_PI_pat<A4_vcmpheqi, int_hexagon_A4_vcmpheqi>;
87 def : T_Q_PI_pat<A4_vcmphgti, int_hexagon_A4_vcmphgti>;
88 def : T_Q_PI_pat<A4_vcmphgtui, int_hexagon_A4_vcmphgtui>;
89 def : T_Q_PI_pat<A4_vcmpweqi, int_hexagon_A4_vcmpweqi>;
90 def : T_Q_PI_pat<A4_vcmpwgti, int_hexagon_A4_vcmpwgti>;
91 def : T_Q_PI_pat<A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui>;
92 def : T_Q_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>;
94 def : T_Q_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
95 def : T_Q_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
96 def : T_Q_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
97 def : T_Q_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>;
98 def : T_Q_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>;
99 def : T_Q_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>;
101 def : T_Q_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>;
102 def : T_Q_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>;
103 def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
105 def : T_Q_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>;
106 def : T_Q_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>;
107 def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
109 def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>;
110 def : T_Q_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
112 def : T_RRR_pat <M4_mpyrr_addr, int_hexagon_M4_mpyrr_addr>;
113 def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
114 def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
115 def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
116 def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
117 def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
118 def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
121 def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>;
122 def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>;
124 def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>;
125 def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>;
127 def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
128 def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>;
131 def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>;
132 def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>;
133 def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>;
134 def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>;
136 def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>;
137 def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>;
140 def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
141 def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
142 def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
143 def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
147 def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
150 def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
153 def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
154 def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
157 def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
158 def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
161 def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
162 def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
165 def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
166 def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
169 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
175 def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
181 def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
184 def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
187 def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
188 def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
191 def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
192 def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
193 def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
194 def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
195 def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
196 def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
197 def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
198 def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
201 def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
202 def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
204 def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
206 def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
207 def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
209 def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
210 def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
211 def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
218 def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
219 def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
226 def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32ImmPred>;
227 def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32ImmPred>;
234 def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32ImmPred>;
235 def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32ImmPred>;
236 def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32ImmPred>;
239 def: T_Q_RR_pat<C4_cmpneq, int_hexagon_C4_cmpneq>;
240 def: T_Q_RR_pat<C4_cmplte, int_hexagon_C4_cmplte>;
241 def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>;
243 def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
244 def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
246 def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>;
247 def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
254 def: T_Q_QQQ_pat<C4_and_and, int_hexagon_C4_and_and>;
255 def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>;
256 def: T_Q_QQQ_pat<C4_and_or, int_hexagon_C4_and_or>;
257 def: T_Q_QQQ_pat<C4_and_orn, int_hexagon_C4_and_orn>;
258 def: T_Q_QQQ_pat<C4_or_and, int_hexagon_C4_or_and>;
259 def: T_Q_QQQ_pat<C4_or_andn, int_hexagon_C4_or_andn>;
260 def: T_Q_QQQ_pat<C4_or_or, int_hexagon_C4_or_or>;
261 def: T_Q_QQQ_pat<C4_or_orn, int_hexagon_C4_or_orn>;
269 def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
270 def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
274 def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>;
275 def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>;
276 def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>;
277 def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>;
278 def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>;
279 def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>;
280 def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>;
281 def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>;
282 def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>;
283 def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
284 def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
286 def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
287 def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>;
288 def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
291 def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
296 def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
297 def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
299 def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
300 def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
302 def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
303 def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
305 def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;