156       if (MI->getOperand(1).isReg())  in isFixedInstr()
161       if (MI->getOperand(0).isReg())  in isFixedInstr()
188     if (!Op.isReg())  in isFixedInstr()
237         if (&MO == &Op || !MO.isReg() || MO.getSubReg())  in partitionRegisters()
397           if (Op.isReg() && Part.count(Op.getReg()))  in isProfitable()
454   assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch");  in collectIndRegsForLoop()
555     if (!Op.isReg()) {  in createHalfInstr()
660   assert(Op0.isReg() && Op1.isImm());  in splitImmediate()
689   assert(Op0.isReg());  in splitCombine()
700   } else if (Op1.isReg()) {  in splitCombine()
709   } else if (Op2.isReg()) {  in splitCombine()
721   assert(Op0.isReg() && Op1.isReg());  in splitExt()
743   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());  in splitShift()
868   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());  in splitAslOr()
1041     if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())  in replaceSubregUses()
1067     if (!Op.isReg() || !Op.isUse())  in collapseRegPairs()