2558   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVEV()  local
2566     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVEV()
2568     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVEV()
2581   return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_ILVEV()
2604   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVOD()  local
2612     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVOD()
2614     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVOD()
2627   return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);  in lowerVECTOR_SHUFFLE_ILVOD()
2651   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVR()  local
2659     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVR()
2661     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVR()
2674   return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_ILVR()
2699   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVL()  local
2707     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVL()
2709     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVL()
2723   return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_ILVL()
2746   SDValue Wt;  in lowerVECTOR_SHUFFLE_PCKEV()  local
2753     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_PCKEV()
2755     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_PCKEV()
2766   return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_PCKEV()
2789   SDValue Wt;  in lowerVECTOR_SHUFFLE_PCKOD()  local
2796     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_PCKOD()
2798     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_PCKOD()
2809   return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_PCKOD()
3066     unsigned Wt = Ws;  in emitCOPY_FW()  local
3070       Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);  in emitCOPY_FW()
3072       BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);  in emitCOPY_FW()
3075     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);  in emitCOPY_FW()
3077     unsigned Wt = RegInfo.createVirtualRegister(  in emitCOPY_FW()  local
3081     BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);  in emitCOPY_FW()
3082     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);  in emitCOPY_FW()
3114     unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);  in emitCOPY_FD()  local
3116     BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);  in emitCOPY_FD()
3117     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);  in emitCOPY_FD()
3140   unsigned Wt = RegInfo.createVirtualRegister(  in emitINSERT_FW()  local
3144   BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)  in emitINSERT_FW()
3151       .addReg(Wt)  in emitINSERT_FW()
3176   unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);  in emitINSERT_FD()  local
3178   BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)  in emitINSERT_FD()
3185       .addReg(Wt)  in emitINSERT_FD()
3262     unsigned Wt = RegInfo.createVirtualRegister(VecRC);  in emitINSERT_DF_VIDX()  local
3263     BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)  in emitINSERT_DF_VIDX()
3267     SrcValReg = Wt;  in emitINSERT_DF_VIDX()