Lines Matching refs:InsIdx

2102   unsigned InsIdx = 0;  in LowerFormalArguments()  local
2105 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) { in LowerFormalArguments()
2129 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT)); in LowerFormalArguments()
2130 ++InsIdx; in LowerFormalArguments()
2133 --InsIdx; in LowerFormalArguments()
2140 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT)); in LowerFormalArguments()
2141 ++InsIdx; in LowerFormalArguments()
2144 --InsIdx; in LowerFormalArguments()
2147 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT)); in LowerFormalArguments()
2185 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) { in LowerFormalArguments()
2186 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2188 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr, in LowerFormalArguments()
2199 ++InsIdx; in LowerFormalArguments()
2202 --InsIdx; in LowerFormalArguments()
2226 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) in LowerFormalArguments()
2227 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P); in LowerFormalArguments()
2229 ++InsIdx; in LowerFormalArguments()
2248 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) { in LowerFormalArguments()
2249 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); in LowerFormalArguments()
2250 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1); in LowerFormalArguments()
2255 InsIdx += 2; in LowerFormalArguments()
2291 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) in LowerFormalArguments()
2292 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt); in LowerFormalArguments()
2297 InsIdx += NumElts; in LowerFormalArguments()
2301 --InsIdx; in LowerFormalArguments()
2311 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) { in LowerFormalArguments()
2312 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2315 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue), in LowerFormalArguments()
2320 Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false, in LowerFormalArguments()
2338 assert(ObjectVT == Ins[InsIdx].VT && in LowerFormalArguments()