Lines Matching refs:IsZExt
158 const TargetRegisterClass *RC, bool IsZExt = true,
165 unsigned DestReg, bool IsZExt);
464 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
492 Opc = (IsZExt ? in PPCEmitLoad()
497 Opc = (IsZExt ? in PPCEmitLoad()
814 bool IsZExt, unsigned DestReg) { in PPCEmitCmp() argument
837 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); in PPCEmitCmp()
838 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
860 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
862 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
866 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
868 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
885 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
1715 unsigned DestReg, bool IsZExt) { in PPCEmitIntExt() argument
1722 if (!IsZExt) { in PPCEmitIntExt()
1817 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
1843 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) in SelectIntExt()
2191 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2198 IsZExt = true; in tryToFoldLoadIntoMI()
2209 IsZExt = true; in tryToFoldLoadIntoMI()
2246 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt)) in tryToFoldLoadIntoMI()