Lines Matching refs:IntRegs
307 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
350 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
352 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
354 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
432 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
454 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
474 def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf),
478 def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf),
495 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
496 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
497 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
498 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
499 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
552 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
553 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
554 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
623 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
627 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
631 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
639 (outs IntRegs:$rd), (ins i32imm:$imm22),
650 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
653 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
657 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
660 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
663 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
667 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
669 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
672 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
676 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
689 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
690 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
691 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
694 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
699 (outs IntRegs:$dst), (ins MEMri:$addr),
704 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
710 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
713 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
715 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
718 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
726 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
730 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
738 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op, IIC_iu_smul>;
930 (outs IntRegs:$dst), (ins MEMrr:$addr),
935 (outs IntRegs:$dst), (ins MEMri:$addr),
981 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
985 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
992 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
996 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
1011 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
1018 (outs IntRegs:$rd), (ins),
1023 (outs IntRegs:$rd), (ins),
1028 (outs IntRegs:$rd), (ins),
1034 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1037 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1044 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1047 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1053 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1056 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1062 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1065 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1316 (outs IntRegs:$rd),
1317 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1324 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1350 : F4_1<0b101100, (outs IntRegs:$rd),
1351 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1356 : F4_2<0b101100, (outs IntRegs:$rd),
1357 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1365 : F4_1<0b101100, (outs IntRegs:$rd),
1366 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1370 : F4_2<0b101100, (outs IntRegs:$rd),
1371 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1475 : F4_1<0b101100, (outs IntRegs:$rd),
1476 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1479 : F4_2<0b101100, (outs IntRegs:$rd),
1480 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1503 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1517 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1518 IntRegs:$swap),
1528 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1529 IntRegs:$swap),
1539 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1540 IntRegs:$swap, i8imm:$asi),
1547 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1557 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1562 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1582 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1589 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1592 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1684 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1686 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1687 (i32 IntRegs:$a2), sub_odd)>;