Lines Matching refs:RegKind
99 unsigned RegKind : 4; member
165 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
170 Op->Mem.RegKind = RegKind; in createMem()
199 bool isReg(RegisterKind RegKind) const { in isReg()
200 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
241 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
242 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
244 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
247 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
248 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); in isMemDisp20()
250 bool isMemDisp12Len8(RegisterKind RegKind) const { in isMemDisp12Len8()
251 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100); in isMemDisp12Len8()
376 const unsigned *Regs, RegisterKind RegKind);
380 RegisterKind RegKind);
581 RegisterKind RegKind) { in parseAddress() argument
624 if (parseRegister(Reg, RegGR, Regs, RegKind)) in parseAddress()
641 const unsigned *Regs, RegisterKind RegKind) { in parseAddress() argument
647 if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind)) in parseAddress()
677 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, in parseAddress()