Lines Matching refs:RESULT

23 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
24 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
33 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
34 ; SI: buffer_store_dword [[RESULT]],
36 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
37 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
51 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
52 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
53 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
69 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
70 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
71 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
72 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
73 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
84 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xffffffe8, [[FFBH]]
85 ; SI: buffer_store_byte [[RESULT]],
151 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
152 ; SI: buffer_store_dword [[RESULT]],
164 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
165 ; SI: buffer_store_dword [[RESULT]],