Lines Matching refs:TMP1

45 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> undef, <16 x i32> zeroini…
46 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
59 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> undef, <32 x i32> <i32 0,…
60 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
71 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
72 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
80 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
81 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
89 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
90 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
98 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
99 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
107 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
108 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
116 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
117 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
125 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
126 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
134 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
135 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
143 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
144 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
152 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
153 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
161 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
162 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
170 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
171 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
180 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
181 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
189 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
190 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
200 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> undef, <16 x i32> <i32 4,…
201 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
209 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> undef, <16 x i32> <i32 0,…
210 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
218 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> undef, <32 x i32> <i32 4,…
219 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
227 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> undef, <32 x i32> <i32 0,…
228 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
271 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> undef, <16 x i32> <i32 0,…
272 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
280 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> undef, <32 x i32> <i32 4,…
281 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
291 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef…
292 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
300 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> %InVec, <32 x i8> <i8 0, i8 undef, i8 undef…
301 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]