Lines Matching refs:TMP1
19 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
20 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
28 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
29 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
45 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
46 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
54 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
55 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
71 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
72 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
80 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
81 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
97 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15,…
98 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
106 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31,…
107 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
127 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
128 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
152 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
153 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
177 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> %v, <i64 15, i64 15>
178 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
202 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
203 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
227 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15,…
228 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
252 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
253 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
281 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, …
282 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
306 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
307 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
331 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> %v, <i64 15, i64 15>
332 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
356 ; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
357 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
381 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, …
382 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
406 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
407 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
435 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
436 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
444 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
445 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
453 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
454 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
470 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
471 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
479 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
480 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
488 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
489 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
505 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
506 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
514 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
515 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
523 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
524 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
540 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15,…
541 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
549 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31,…
550 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
558 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31,…
559 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
579 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
580 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
612 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
613 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
645 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> %v, <i64 15, i64 15>
646 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
670 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15…
671 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
703 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15,…
704 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
736 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
737 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
765 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, …
766 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
798 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
799 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
831 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> %v, <i64 15, i64 15>
832 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
856 ; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
857 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
889 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, …
890 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
922 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
923 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
959 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
960 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
968 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i…
969 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
977 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 undef>
978 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
986 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 undef, i32 31, i32 31, i32 31, i32 31, i32 …
987 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
995 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
996 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1005 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> %v, <i32 0, i32 undef, i32 16, i32 24, i32 31, i32 2…
1006 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1035 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
1036 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1044 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i…
1045 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1053 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> …
1054 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1062 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i…
1063 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1087 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
1088 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1097 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> %v, <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 2…
1098 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1123 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> %v, <i64 0, i64 8>
1124 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1132 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> %v, <i64 0, i64 8, i64 16, i64 31>
1133 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1141 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> …
1142 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1150 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i…
1151 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1175 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> %v, <i64 0, i64 undef>
1176 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1185 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> %v, <i64 undef, i64 8, i64 16, i64 31>
1186 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1215 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
1216 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1224 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i3…
1225 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1233 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> …
1234 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1242 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i…
1243 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1267 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
1268 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1277 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> %v, <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24…
1278 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1303 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> %v, <i64 0, i64 8>
1304 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1312 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> %v, <i64 0, i64 8, i64 16, i64 31>
1313 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1321 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> …
1322 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1330 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i…
1331 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1355 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> %v, <i64 0, i64 undef>
1356 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1365 ; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> %v, <i64 undef, i64 8, i64 16, i64 31>
1366 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1379 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %…
1380 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
1389 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> %a to <8 x i16>
1390 …NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> [[TMP1]])
1401 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> %…
1402 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1411 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> %a to <4 x i32>
1412 …NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> [[TMP1]])
1423 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16>…
1424 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
1433 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> %…
1434 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1443 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> %…
1444 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
1453 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> %…
1454 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1463 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> %…
1464 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1473 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16>…
1474 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
1483 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> %a to <8 x i16>
1484 …XT: [[TMP2:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> [[TMP1]])
1495 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> %…
1496 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1505 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> %a to <4 x i32>
1506 …NEXT: [[TMP2:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> [[TMP1]])
1517 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> %…
1518 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
1527 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> %…
1528 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
1537 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> %…
1538 ; CHECK-NEXT: ret <4 x i32> [[TMP1]]
1547 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> %…
1548 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
1557 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16>…
1558 ; CHECK-NEXT: ret <16 x i16> [[TMP1]]
1567 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> %…
1568 ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
1577 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> %…
1578 ; CHECK-NEXT: ret <4 x i64> [[TMP1]]