Lines Matching refs:TMP1

6 ; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0
7 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]])
31 ; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
32 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]])
60 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i64> %a, %b
61 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
70 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <2 x i64> %a, %b
71 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
80 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sle <2 x i64> %a, %b
81 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
90 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ule <2 x i64> %a, %b
91 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
100 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> %a, %b
101 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
110 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> %a, %b
111 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
120 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sge <4 x i32> %a, %b
121 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
130 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge <4 x i32> %a, %b
131 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
140 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> %a, %b
141 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
150 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> %a, %b
151 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
160 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <8 x i16> %a, %b
161 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
170 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <8 x i16> %a, %b
171 ; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>