Lines Matching refs:br32
59 static inline u32 br32(const struct b44_private *bp, u32 reg) in br32() function
104 u32 pending = br32(bp, B44_DMATX_STAT); in pending_tx_index()
118 u32 pending = br32(bp, B44_DMARX_STAT); in pending_rx_index()
135 u32 val = br32(bp, reg); in b44_wait_bit()
166 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK); in ssb_get_core_rev()
172 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
186 val = br32(bp, B44_SBINTVEC); in ssb_pci_setup()
190 val = br32(bp, SSB_PCI_TRANS_2); in ssb_pci_setup()
202 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET) in ssb_core_disable()
229 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR) in ssb_core_reset()
232 val = br32(bp, B44_SBIMSTATE); in ssb_core_reset()
271 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) in b44_chip_reset()
294 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) { in b44_chip_reset()
298 u32 val = br32(bp, B44_DEVCTRL); in b44_chip_reset()
370 val = br32(bp, B44_ENET_CTRL); in b44_init_hw()
499 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA; in b44_phy_read()
575 val = br32(bp, B44_CAM_CTRL); in b44_set_mac_addr()
616 val = br32(bp, B44_RXCONFIG); in b44_set_rx_mode()
626 val = br32(bp, B44_CAM_CTRL); in b44_set_rx_mode()
904 istat = br32(bp, B44_ISTAT); in b44_poll()