Lines Matching refs:bw32

65 static inline void bw32(const struct b44_private *bp, u32 reg, u32 val)  in bw32()  function
188 bw32(bp, B44_SBINTVEC, val); in ssb_pci_setup()
192 bw32(bp, SSB_PCI_TRANS_2, val); in ssb_pci_setup()
205 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
209 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
213 bw32(bp, B44_SBTMSLOW, SSB_CORE_DOWN); in ssb_core_disable()
225 bw32(bp, B44_SBTMSLOW, mask); in ssb_core_reset()
230 bw32(bp, B44_SBTMSHIGH, 0); in ssb_core_reset()
234 bw32(bp, B44_SBIMSTATE, val & ~SBIMSTATE_BAD); in ssb_core_reset()
237 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
240 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
261 bw32(bp, B44_RCV_LAZY, 0); in b44_chip_reset()
263 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE); in b44_chip_reset()
267 bw32(bp, B44_DMATX_CTRL, 0); in b44_chip_reset()
275 bw32(bp, B44_DMARX_CTRL, 0); in b44_chip_reset()
289 bw32(bp, B44_MDIO_CTRL, in b44_chip_reset()
295 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL); in b44_chip_reset()
300 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR)); in b44_chip_reset()
313 bw32(bp, B44_IMASK, 0); in b44_halt()
317 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN); in b44_halt()
346 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL); in b44_init_hw()
347 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT)); in b44_init_hw()
353 bw32(bp, B44_RXMAXLEN, B44_MAX_MTU + ETH_HLEN + 8 + RX_HEADER_LEN); in b44_init_hw()
354 bw32(bp, B44_TXMAXLEN, B44_MAX_MTU + ETH_HLEN + 8 + RX_HEADER_LEN); in b44_init_hw()
356 bw32(bp, B44_TX_HIWMARK, TX_HIWMARK_DEFLT); in b44_init_hw()
358 bw32(bp, B44_DMARX_CTRL, CTRL_MASK); in b44_init_hw()
360 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE); in b44_init_hw()
361 bw32(bp, B44_DMATX_ADDR, VIRT_TO_B44(bp->tx)); in b44_init_hw()
363 bw32(bp, B44_DMARX_CTRL, CTRL_MASK); in b44_init_hw()
364 bw32(bp, B44_DMARX_ADDR, VIRT_TO_B44(bp->rx)); in b44_init_hw()
365 bw32(bp, B44_DMARX_PTR, B44_RX_RING_LEN_BYTES); in b44_init_hw()
367 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); in b44_init_hw()
371 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE)); in b44_init_hw()
395 bw32(bp, B44_DMARX_PTR, idx * sizeof(struct dma_desc)); in b44_populate_rx_descriptor()
496 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); in b44_phy_read()
497 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | argv)); in b44_phy_read()
515 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); in b44_phy_write()
516 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | argv)); in b44_phy_write()
555 bw32(bp, B44_CAM_DATA_LO, val); in b44_cam_write()
561 bw32(bp, B44_CAM_DATA_HI, val); in b44_cam_write()
564 bw32(bp, B44_CAM_CTRL, val); in b44_cam_write()
573 bw32(bp, B44_CAM_CTRL, 0); in b44_set_mac_addr()
576 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); in b44_set_mac_addr()
625 bw32(bp, B44_RXCONFIG, val); in b44_set_rx_mode()
627 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); in b44_set_rx_mode()
731 bw32(bp, B44_IMASK, enable ? IMASK_DEF : IMASK_DISABLE); in b44_irq()
813 bw32(bp, B44_DMATX_PTR, cur * sizeof(struct dma_desc)); in b44_transmit()
925 bw32(bp, B44_ISTAT, 0); in b44_poll()