106 	pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);  in tg3_write_indirect_reg32()
107 	pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);  in tg3_write_indirect_reg32()
133 	pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);  in tg3_write_mem()
134 	pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_write_mem()
137 	pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_write_mem()
142 	pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);  in tg3_read_mem()
143 	pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_read_mem()
146 	pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_read_mem()
522 	pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);  in tg3_set_power_state_0()
524 	pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);  in tg3_set_power_state_0()
529 	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);  in tg3_set_power_state_0()
1600 	pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);  in tg3_chip_reset()
1605 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_chip_reset()
1613 	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);  in tg3_chip_reset()
1615 	pci_restore_state(tp->pdev, tp->pci_cfg_state);  in tg3_chip_reset()
1618 	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);  in tg3_chip_reset()
1620 	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);  in tg3_chip_reset()
2714 	pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);  in tg3_get_invariants()
2715 	pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);  in tg3_get_invariants()
2737 	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
2741 	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
2749 	pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);  in tg3_get_invariants()
2756 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
2759 	pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);  in tg3_get_invariants()
2761 		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);  in tg3_get_invariants()
2764 	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);  in tg3_get_invariants()
2793 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);  in tg3_get_invariants()
2799 	val = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);  in tg3_get_invariants()
2878 			(tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&  in tg3_get_invariants()
2879 			((tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901) ||  in tg3_get_invariants()
2880 				(tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2)))) {  in tg3_get_invariants()
2912 	if (PCI_FUNC(tp->pdev->devfn) == 0)  in tg3_get_device_address()
3264 static int tg3_probe ( struct nic *nic, struct pci_device *pdev ) {  in tg3_probe()  argument
3272 	adjust_pci_device(pdev);  in tg3_probe()
3275         nic->ioaddr = pdev->ioaddr;  in tg3_probe()
3278 	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);  in tg3_probe()
3283 	tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);  in tg3_probe()
3288 	tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);  in tg3_probe()
3290 	tp->pdev       = pdev;  in tg3_probe()
3347 	pci_save_state(tp->pdev, tp->pci_cfg_state);  in tg3_probe()