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Lines Matching refs:tr32

114 #define tr32(reg)		readl(tg3.regs + (reg))  macro
121 tr32(reg); in tw32_carefully()
128 tr32(reg); in tw32_mailbox2()
160 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); in tg3_switch_clocks()
200 frame_val = tr32(MAC_MI_COM); in tg3_readphy()
204 frame_val = tr32(MAC_MI_COM); in tg3_readphy()
239 frame_val = tr32(MAC_MI_COM); in tg3_writephy()
242 frame_val = tr32(MAC_MI_COM); in tg3_writephy()
991 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
992 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); in tg3_fiber_aneg_smachine()
1236 (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) { in tg3_setup_fiber_phy()
1277 if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) { in tg3_setup_fiber_phy()
1332 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_phy()
1338 (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) { in tg3_setup_fiber_phy()
1358 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_phy()
1364 if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) in tg3_setup_fiber_phy()
1388 if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) { in tg3_setup_fiber_phy()
1453 val = tr32(ofs); in tg3_stop_block()
1456 tr32(ofs); in tg3_stop_block()
1460 val = tr32(ofs); in tg3_stop_block()
1508 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
1513 (unsigned int) tr32(MAC_TX_MODE)); in tg3_abort_hw()
1521 val = tr32(FTQ_RESET); in tg3_abort_hw()
1555 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_chip_reset()
1569 if (tr32(0x7e2c) == 0x60) { in tg3_chip_reset()
1641 val = tr32(GRC_RX_CPU_EVENT); in tg3_stop_fw()
1647 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14))) in tg3_stop_fw()
1861 val = tr32(TG3PCI_PCISTATE); in tg3_setup_hw()
1939 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_setup_hw()
1951 if (tr32(FTQ_RESET) == 0x00000000) in tg3_setup_hw()
2075 if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_setup_hw()
2085 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_setup_hw()
2101 tr32(MAILBOX_INTERRUPT_0); in tg3_setup_hw()
2113 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) && in tg3_setup_hw()
2125 val = tr32(TG3PCI_X_CAPS); in tg3_setup_hw()
2248 tr32(MAC_LOW_WMARK_MAX_RX_FRAME); in tg3_setup_hw()
2305 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); in tg3_nvram_init()
2309 uint32_t nvcfg1 = tr32(NVRAM_CFG1); in tg3_nvram_init()
2337 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | in tg3_nvram_read_using_eeprom()
2348 tmp = tr32(GRC_EEPROM_ADDR); in tg3_nvram_read_using_eeprom()
2358 *val = tr32(GRC_EEPROM_DATA); in tg3_nvram_read_using_eeprom()
2379 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_read()
2394 !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE)) in tg3_nvram_read()
2397 (tr32(NVRAM_CMD) & NVRAM_CMD_DONE)) in tg3_nvram_read()
2405 *val = bswap_32(tr32(NVRAM_RDDATA)); in tg3_nvram_read()
2857 grc_misc_cfg = tr32(GRC_MISC_CFG); in tg3_get_invariants()
2941 hi = tr32(MAC_ADDR_0_HIGH); in tg3_get_device_address()
2942 lo = tr32(MAC_ADDR_0_LOW); in tg3_get_device_address()
2989 uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_setup_dma()
3056 mac_stat = tr32(MAC_STATUS); in tg3_poll_link()
3093 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); in tg3_ack_irqs()