110 #define tw32(reg,val)		tg3_write_indirect_reg32((reg),(val))  macro
120 	tw32(reg, val);  in tw32_carefully()
151 	tw32(TG3PCI_MISC_HOST_CTRL,  in tg3_disable_ints()
865 		tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);  in tg3_setup_copper_phy()
1050 		tw32(MAC_TX_AUTO_NEG, 0);  in tg3_fiber_aneg_smachine()
1074 		tw32(MAC_TX_AUTO_NEG, ap->txconfig);  in tg3_fiber_aneg_smachine()
1089 		tw32(MAC_TX_AUTO_NEG, ap->txconfig);  in tg3_fiber_aneg_smachine()
1287 			tw32(MAC_TX_AUTO_NEG, 0);  in tg3_setup_fiber_phy()
1413 		tw32(MAC_TX_LENGTHS,  in tg3_setup_phy()
1418 		tw32(MAC_TX_LENGTHS,  in tg3_setup_phy()
1455 	tw32(ofs, val);  in tg3_stop_block()
1528 	tw32(FTQ_RESET, val);  in tg3_abort_hw()
1553 			tw32(NVRAM_SWARB, SWARB_REQ_SET1);  in tg3_chip_reset()
1570 			tw32(0x7e2c, 0x20);  in tg3_chip_reset()
1573 			tw32(GRC_MISC_CFG, (1 << 29));  in tg3_chip_reset()
1589 	  tw32(GRC_MISC_CFG, 0x20000000) ;  in tg3_chip_reset()
1593 	tw32(GRC_MISC_CFG, val);  in tg3_chip_reset()
1622 	tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);  in tg3_chip_reset()
1628 		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);  in tg3_chip_reset()
1631 	tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);  in tg3_chip_reset()
1643 		tw32(GRC_RX_CPU_EVENT, val);  in tg3_stop_fw()
1709 		tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);  in __tg3_set_mac_addr()
1710 		tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);  in __tg3_set_mac_addr()
1717 			tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);  in __tg3_set_mac_addr()
1718 			tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);  in __tg3_set_mac_addr()
1728 	tw32(MAC_TX_BACKOFF_SEED, addr_high);  in __tg3_set_mac_addr()
1796 		tw32(_table[0], _table[1]); \
1822 	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_setup_hw()
1837 	tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */  in tg3_setup_hw()
1863 		tw32(TG3PCI_PCISTATE, val);  in tg3_setup_hw()
1886 	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_setup_hw()
1896 	tw32(GRC_MODE,  in tg3_setup_hw()
1901 	tw32(GRC_MISC_CFG,  in tg3_setup_hw()
1909 		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);  in tg3_setup_hw()
1911 			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);  in tg3_setup_hw()
1913 			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);  in tg3_setup_hw()
1914 		tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);  in tg3_setup_hw()
1915 		tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);  in tg3_setup_hw()
1918 		tw32(BUFMGR_MB_RDMA_LOW_WATER,  in tg3_setup_hw()
1920 		tw32(BUFMGR_MB_MACRX_LOW_WATER,  in tg3_setup_hw()
1922 		tw32(BUFMGR_MB_HIGH_WATER,  in tg3_setup_hw()
1925 		tw32(BUFMGR_MB_RDMA_LOW_WATER,  in tg3_setup_hw()
1927 		tw32(BUFMGR_MB_MACRX_LOW_WATER,  in tg3_setup_hw()
1929 		tw32(BUFMGR_MB_HIGH_WATER,  in tg3_setup_hw()
1932 	tw32(BUFMGR_DMA_LOW_WATER,  in tg3_setup_hw()
1934 	tw32(BUFMGR_DMA_HIGH_WATER,  in tg3_setup_hw()
1937 	tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);  in tg3_setup_hw()
1948 	tw32(FTQ_RESET, 0xffffffff);  in tg3_setup_hw()
1949 	tw32(FTQ_RESET, 0x00000000);  in tg3_setup_hw()
2002 		tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,   in tg3_setup_hw()
2006 			tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,  in tg3_setup_hw()
2083 	tw32(HOSTCC_MODE, 0);  in tg3_setup_hw()
2136 		tw32(TG3PCI_X_CAPS, val);  in tg3_setup_hw()
2214 		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,  in tg3_setup_hw()
2216 		tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,  in tg3_setup_hw()
2233 	tw32(MAC_LED_CTRL, 0);  in tg3_setup_hw()
2234 	tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);  in tg3_setup_hw()
2242 		tw32(MAC_SERDES_CFG, 0x616000);  in tg3_setup_hw()
2247 	tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);  in tg3_setup_hw()
2255 	tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);  in tg3_setup_hw()
2256 	tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);  in tg3_setup_hw()
2257 	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);  in tg3_setup_hw()
2258 	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);  in tg3_setup_hw()
2268 	case 16:	tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);  in tg3_setup_hw()
2269 	case 15:	tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);  in tg3_setup_hw()
2270 	case 14:	tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);  in tg3_setup_hw()
2271 	case 13:	tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);  in tg3_setup_hw()
2272 	case 12:	tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);  in tg3_setup_hw()
2273 	case 11:	tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);  in tg3_setup_hw()
2274 	case 10:	tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);  in tg3_setup_hw()
2275 	case 9:		tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);  in tg3_setup_hw()
2276 	case 8:		tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);  in tg3_setup_hw()
2277 	case 7:		tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);  in tg3_setup_hw()
2278 	case 6:		tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);  in tg3_setup_hw()
2279 	case 5:		tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);  in tg3_setup_hw()
2296 	tw32(GRC_EEPROM_ADDR,  in tg3_nvram_init()
2317 			tw32(NVRAM_CFG1, nvcfg1);  in tg3_nvram_init()
2340 	tw32(GRC_EEPROM_ADDR,  in tg3_nvram_read_using_eeprom()
2377 	tw32(NVRAM_SWARB, SWARB_REQ_SET1);  in tg3_nvram_read()
2384 	tw32(NVRAM_ADDR, offset);  in tg3_nvram_read()
2385 	tw32(NVRAM_CMD,  in tg3_nvram_read()
2401 		tw32(NVRAM_SWARB, SWARB_REQ_CLR1);  in tg3_nvram_read()
2406 	tw32(NVRAM_SWARB, 0x20);  in tg3_nvram_read()
2838 	tw32(GRC_MODE, tp->grc_mode);  in tg3_get_invariants()
2843 	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_get_invariants()
2958 	tw32(TG3PCI_CLOCK_CTRL, 0);  in tg3_setup_dma()
3010 	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_setup_dma()